參數(shù)資料
型號(hào)： SYM53C825AE
廠商： LSI Corporation
英文描述： PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器)
中文描述： 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器）
文件頁(yè)數(shù)： 135/225頁(yè)
文件大小： 1237K
代理商： SYM53C825AE
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Instruction Set of the I/O Processor
Block Move Instructions
SYM53C825A/825AE Data Manual
6-7
an odd byte boundary, the SYM53C825A will
store the last byte in the SCSI Wide Residue
Data Register during a receive operation, or in
the SCSI Output Data Latch Register during a
send operation. T his byte will be combined
with the first byte from the subsequent transfer
so that a wide transfer can be completed.
5. If the SCSI phase bits do not match the value
stored in the SSTAT 1 register, the
SYM53C825A generates a phase mismatch
interrupt and the instruction is not executed.
6. During a Message Out phase, after the
SYM53C825A has performed a select with
Attention (or SAT N/ has been manually
asserted with a Set AT N instruction), the
SYM53C825A will deassert SAT N/ during the
final SREQ/SACK handshake.
7. When the SYM53C825A is performing a block
move for Message In phase, it will not deassert
the SACK / signal for the last SREQ/SACK
handshake. T he SACK signal must be cleared
using the Clear SACK I/O instruction.
Bits 26-24 SCSI Phase
T his 3-bit field defines the desired SCSI infor-
mation transfer phase. When the
SYM53C825A operates in initiator mode,
these bits are compared with the latched SCSI
phase bits in the SSTAT 1 register. When the
SYM53C825A operates in target mode, the
SYM53C825A asserts the phase defined in this
field. T he following table describes the possible
combinations and the corresponding SCSI
phase.
Bits 23-0 Transfer Counter
T his 24-bit field specifies the number of data
bytes to be moved between the SYM53C825A
and system memory. T he field is stored in the
DBC register. When the SYM53C825A trans-
fers data to/from memory, the DBC register is
decremented by the number of bytes trans-
ferred. In addition, the DNAD register is
incremented by the number of bytes trans-
ferred. T his process is repeated until the DBC
register has been decremented to zero. At that
time, the SYM53C825A fetches the next
instruction.
If bit 28 is set, indicating table indirect
addressing, this field is not used. T he byte
count is instead fetched from a table pointed to
by the DSA register.
Second Dword
Bits 31-0 Start Address
T his 32-bit field specifies the starting address
of the data to be moved to/from memory. T his
field is copied to the DNAD register. When the
SYM53C825A transfers data to or from mem-
ory, the DNAD register is incremented by the
number of bytes transferred.
When bit 29 is set, indicating indirect address-
ing, this address is a pointer to an address in
memory that points to the data location. When
bit 28 is set, indicating table indirect address-
ing, the value in this field is an offset into a
table pointed to by the DSA. T he table entry
contains byte count and address information.
MSG
C/D
I/O
SCSI Phase
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Data out
Data in
Command
Status
Reserved out
Reserved in
Message out
1
1
1
Message in
MSG
C/D
I/O
SCSI Phase
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