![](http://datasheet.mmic.net.cn/390000/SYM53C825A_datasheet_16836334/SYM53C825A_149.png)
Instruction Set of the I/O Processor
Memory Move Instructions
SYM53C825A/825AE Data Manual
6-21
Bit 24
Note: T his bit has no effect unless the Pre-fetch
Enable bit in the DCNT L register is set.
For information on SCRIPT S instruction
prefetching, see Chapter 2.
When this bit is set, the SYM53C825A performs a
Memory Move without flushing the prefetch unit.
When this bit is clear, the Memory Move instruc-
tion automatically flushes the prefetch unit. T he
No Flush option should be used if the source and
destination are not within four instructions of the
current Memory Move instruction.
Bits 23-0 Transfer Count
T he number of bytes to be transferred is stored
in the lower 24 bits of the first instruction
word.
No Flush
Read/Write System
Memory from a Script
By using the Memory Move instruction, single or
multiple register values may be transferred to or
from system memory.
Because the SYM53C825A will respond to
addresses as defined in the Base I/O or Base Mem-
ory registers, it could be accessed during a Mem-
ory Move operation if the source or destination
address decodes to within the chip’s register space.
If this occurs, the register indicated by the lower
seven bits of the address is taken to bethe data
source or destination. In this way, register values
can be saved to system memory and later restored,
and SCRIPT S can make decisions based on data
values in system memory. T he SFBR is not writ-
able via the CPU, and therefore not by a Memory
Move. However, it can be loaded via SCRIPT S
Read/Write operations. To load the SFBR with a
byte stored in system memory, the byte must first
be moved to an intermediate SYM53C825A regis-
ter (for example, a SCRAT CH register), and then
to the SFBR.
T he same address alignment restrictions apply to
register access operations as to normal memory-to-
memory transfers.
Second Dword
Bits 31-0, DSPS Register
T hese bits contain the source address of the
Memory Move.
T hird Dword
Bits 31-0, T E MP Register
T hese bits contain the destination address for
the Memory Move.