參數(shù)資料
型號(hào)： SYM53C825AE
廠商： LSI Corporation
英文描述： PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器)
中文描述： 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器）
文件頁(yè)數(shù)： 151/225頁(yè)
文件大小： 1237K
代理商： SYM53C825AE
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Instruction Set of the I/O Processor
Load and Store Instructions
SYM53C825A/825AE Data Manual
6-23
Load and Store
Instructions
T he Load and Store instructions provide a more
efficient way to move data from/to memory to/from
an internal register in the chip without using the
normal memory move instruction.
T he load and store instructions are represented by
two-dword op codes. T he first dword contains the
DCMD and DBC register values. T he second
dword contains the DSPS value. T his is either the
actual memory location of where to load or store,
or the offset from the DSA, depending on the
value of Bit 28 (DSA Relative).
A maximum of 4 bytes may be moved with these
instructions. T he register address and memory
address must have the same byte alignment, and
the count set such that it does not cross dword
boundaries. T he destination memory address in
the Store instruction and the source memory
address of the Load instruction may not map back
to the operating register set of the chip. T his
excludes the SCRIPT S RAM and ROM memory
spaces. If it does, a PCI read/write cycle will occur
(the data does not actually transfer to/from the
chip), and the chip will issue an interrupt (Illegal
Instruction Detected) immediately following.
T he SIOM and DIOM bits in the DMODE regis-
ter determine whether the destination or source
address of the instruction is in Memory space or
I/O space, as illustrated in the following table. T he
Load/Store utilizes the PCI commands for I/O
READ and I/O WRIT E to access the I/O space.
First Dword
Bits 31-29, Instruction Type
T hese bits should be 111, indicating the Load
and Store instruction.
Bit 28, DSA Relative
When this bit is clear, the value in the DSPS is
the actual 32-bit memory address to perform
the load/store to/from. When this bit is set, the
chip determines the memory address to per-
form the load/store to/from by adding the 24-
bit signed offset value in the DSPS to the DSA.
Bits 27-26, Reserved
Bit 25, No Flush (Store instruction only)
Note: T his bit has no effect unless the Pre-fetch
Enable bit in the DCNT L register is set.
For information on SCRIPT S instruction
prefetching, see Chapter 2.
When this bit is set, the SYM53C825A per-
forms a Store without flushing the prefetch
unit. When this bit is clear, the Store instruc-
tion automatically flushes the prefetch unit. No
Flush should be used if the source and destina-
tion are not within four instructions of the cur-
rent Store instruction. T his bit has no effect on
the Load instruction.
Bit 24, Load/Store
When this bit is set, the instruction is a Load.
When cleared, it is a Store.
Bit 23, Reserved
Bits 22-16, Register Address
A6-A0 select the register to load/store to/from
within the SYM53C825A.
Note: It is not possible to Load the SFBR
register, although it is possible to store the
SFBR contents to another location.
Bits 15-3, Reserved
Bits 2-0, Byte Count
T his value is the number of bytes to load/store.
Bits A1, A0
Number of bytes allowed to load/
store
00
One, two, three or four
01
One, two, or three
10
One or two
11
One
Bit
Source
Destination
SIOM (Load)
DIOM (Store)
memory
register
register
memory
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