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參數(shù)資料
| 型號(hào)： | SYM53C825AE |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器） |
| 文件頁(yè)數(shù)： | 69/225頁(yè) |
| 文件大?。?/td> | 1237K |
| 代理商： | SYM53C825AE |
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Signal Descriptions
Additional Interface Pins
SYM53C825A/825AE Data Manual
4-9
Table 4-8: Additional Interface Pins
Symbol
Pin No.
Type
Description
T EST IN
(Not avail-
able on
53C825AJ)
57, NA
I
Test In. When this pin is driven low, the SYM53C825A connects
all inputs and outputs to an “AND tree.” T he SCSI control signals
and data lines are not connected to the “AND tree.” T he output of
the “AND tree” is connected to the Test Out pin. T his allows man-
ufacturers to verify chip connectivity and determine exactly which
pins are not properly attached. When the T EST IN pin is driven
low, internal pull-ups are enabled on all input, output, and bidirec-
tional pins, all outputs and bidirectional signals will be tri-stated,
and the MAC/_T EST OUT pin will be enabled. Connectivity can
be tested by driving one of the SYM53C825A pins low. T he MAC/
_T EST OUT pin should respond by also driving low.
General Purpose I/O pin. Optionally, when driven low, this pin
indicates that the next bus request will be for an op code fetch. T his
pin powers up as a general purpose input.
T his pin has two specific purposes in the Symbios SDMS software.
SDMS uses it to toggle SCSI device LEDs, turning on the LED
whenever the SYM53C825A is on the SCSI bus. SDMS drives this
pin low to turn on the LED, or drives it high to turn off the LED.
T his signal can also be used as data I/O for serial EEPROM access.
In this case it is used with the GPIO0 pin, which serves as a clock,
and the pin can be controlled from PCI configuration register 35h
or observed from the GPREG operating register, at address 07h.
General purpose I/O pin. Optionally, when driven low, indicates
that the SYM53C825A is bus master. T his pin powers up as a gen-
eral purpose input.
Symbios SDMS software supports use of this signal in serial
EEPROM applications, when enabled, in combination with the
GPIO0 pin. When this signal is used as a clock for serial EEPROM
access, the GPIO1 pin serves as data, and the pin is controlled
from PCI configuration register 35h.
General purpose I/O pins. GPIO4 powers up as an output. It can
be used as the enable line for V
PP
, the 12 Volt power supply to the
external flash memory interface. GPIO3 powers up as an input.
Symbios SDMS software uses GPIO3 to detect a differential
board. If the pin is pulled low externally, the board will be config-
ured by SDMS as a differential board. If it is pulled high or left
floating, SDMS will configure it as a single-ended board. T he Sym-
bios PCI to SCSI host adapters use the GPIO4 pin in the process
of flashing a new SDMS ROM.
T he Differential Sense pin detects the presence of a single-ended
device on a differential system. When external differential trans-
ceivers are used and a zero is detected on this pin, all chip SCSI
outputs will be tri-stated to avoid damage to the transceivers. T his
pin should be tied high during single-ended operation. T he normal
value of this pin is 1.
GPIO0_
FET CH/
53
I/O
GPIO1_
MAST ER/
54
I/O
GPIO4-3
71, 70
I/O
DIFFSENS
72
I
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