參數(shù)資料
型號(hào)： SYM53C825AE
廠商： LSI Corporation
英文描述： PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器)
中文描述： 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器）
文件頁(yè)數(shù)： 40/225頁(yè)
文件大小： 1237K
代理商： SYM53C825AE
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2-20
SYM53C825A/825AE Data Manual
Functional Description
Interrupt Handling
If you are polling the ISTAT instead of using hard-
ware interrupts, then masking a fatal interrupt will
make no difference since the SIP and DIP bits in
the ISTAT inform the system of interrupts, not the
IRQ/ pin.
Masking an interrupt after IRQ/ is asserted will not
cause IRQ/ to be deasserted.
Stacked Interrupts
T he SYM53C825A stacks interrupts if they occur
one after the other. If the SIP or DIP bits in the
ISTAT register are set (first level), then there is
already at least one pending interrupt, and any
future interrupts will be stacked in extra registers
behind the SIST 0, SIST 1, and DSTAT registers
(second level). When two interrupts have occurred
and the two levels of the stack are full, any further
interrupts will set additional bits in the extra regis-
ters behind SIST 0, SIST 1, and DSTAT. When the
first level of interrupts are cleared, all the inter-
rupts that came in afterward will move into the
SIST 0, SIST 1, and DSTAT. After the first inter-
rupt is cleared by reading the appropriate register,
the IRQ/ pin will be deasserted for a minimum of
three CLK s; the stacked interrupt(s) will move
into the SIST 0, SIST 1, or DSTAT ; and the IRQ/
pin will be asserted once again.
Since a masked non-fatal interrupt will not set the
SIP or DIP bits, interrupt stacking will not occur.
A masked, non-fatal interrupt will still post the
interrupt in SIST 0, but will not assert the IRQ/
pin. Since no interrupt is generated, future inter-
rupts will move right into the SIST 0 or SIST 1
instead of being stacked behind another interrupt.
When another condition occurs that generates an
interrupt, the bit corresponding to the earlier
masked non-fatal interrupt will still be set.
A related situation to interrupt stacking is when
two interrupts occur simultaneously. Since stack-
ing does not occur until the SIP or DIP bits are
set, there is a small timing window in which multi-
ple interrupts can occur but will not be stacked.
T hese could be multiple SCSI interrupts (SIP set),
multiple DMA interrupts (DIP set), or multiple
SCSI and multiple DMA interrupts (both SIP and
DIP set).
As previously mentioned, DMA interrupts will not
attempt to flush the FIFOs before generating the
interrupt. It is important to set either the Clear
DMA FIFO (CLF) and Clear SCSI FIFO (CSF)
bits if a DMA interrupt occurs and the DMA
FIFO Empty (DFE) bit is not set. T his is because
any future SCSI interrupts will not be posted until
the DMA FIFO is clear of data. T hese ‘locked out’
SCSI interrupts will be posted as soon as the
DMA FIFO is empty.
Halting in an
Orderly Fashion
When an interrupt occurs, the SYM53C825A will
attempt to halt in an orderly fashion.
I
If the interrupt occurs in the middle of an
instruction fetch, the fetch will be completed,
except in the case of a Bus Fault. Execution
will not begin, but the DSP will point to the
next instruction since it is updated when the
current instruction is fetched.
I
If the DMA direction is a write to memory and
a SCSI interrupt occurs, the SYM53C825A
will attempt to flush the DMA FIFO to
memory before halting. Under any other
circumstances only the current cycle will be
completed before halting, so the DFE bit in
DSTAT should be checked to see if any data
remains in the DMA FIFO.
I
SCSI SREQ/SACK handshakes that have
begun will be completed before halting.
I
T he SYM53C825A will attempt to clean up
any outstanding synchronous offset before
halting.
I
In the case of Transfer Control Instructions,
once instruction execution begins it will
continue to completion before halting.
I
If the instruction is a JUMP/CALL WHEN/IF
<phase>, the DSP will be updated to the
transfer address before halting.
I
All other instructions may halt before
completion.
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