參數(shù)資料
型號(hào): ST7FLCD1G9M1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO28
封裝: ROHS COMPLIANT, SO-28
文件頁數(shù): 83/96頁
文件大小: 846K
代理商: ST7FLCD1G9M1
Infrared Preprocessor (IFR)
ST7FLCD1
The IFR input signal is preprocessed by a spike filter. This filter removes all pulses with a positive
level that lasts less than 2 s or 160 s, depending on the FLSEL bit. The negative level can be of
any duration and is never filtered out.
Note:
If the interrupt is enabled but no signal is detected, an interrupt occurs every 20.4 ms.
15.3
Register Description
INFRA RED DATA REGISTER (IFRDR)
Read/Write
Reset Value: (00h)
Bits [7:0] = IR[7:0] Infra red pulse width
The 8-bit counter value is transferred in this register when an expected edge occurs on the IFR pin
or when the counter overflows. A write to this register resets the internal overflow flag.
INFRA RED CONTROL REGISTER (IFRCR)
Read/Write
Reset Value: (00h)
Bits [7:5] = Reserved. Forced by hardware to 0.
Bit 4 = ITE Interrupt enable
0
Interrupt disabled
1
Interrupt enabled. It is generated when an edge (falling and/or rising depending on bits POSED
and NEGED) occurs or after a counter overflow.
Bit 3 = FLSEL Spike filter pulse width selection
0
Filter positive pulses narrower than 2 s
1
Filter positive pulses narrower than 160 s
Bits [2:1] = POSED, NEGED Edge selection for the duration measurement
Bit 0 = Reserved. Forced by hardware to 0.
765
432
10
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0
765
432
10
0
ITE
FLSEL
POSED
NEGED
0
Table 30: Duration Measurement
POSED
NEGED
Count latch at...
0
When count reaches 255
0
1
Negative transition of IFR or when count reaches 255
1
0
Positive transition of IFR or when count reaches 255
1
Positive or negative transition of IFR or when count reached 255
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