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參數(shù)資料
| 型號： | ST7FLCD1G9M1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | ROHS COMPLIANT, SO-28 |
| 文件頁數(shù)： | 38/96頁 |
| 文件大?。?/td> | 846K |
| 代理商： | ST7FLCD1G9M1 |
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ST7FLCD1
PWM Generator
8PWM Generator
8.1
Introduction
This PWM on-chip peripheral consists of two blocks, each one with its own 8-bit auto-reload
counter.
The first block (Block A) outputs up to 4 separate PWM signals at the same frequency. The second
block (Block B) outputs up to 2 separate PWM signals at another frequency.
Each PWM output may be enabled or disabled independently of the other. The polarity of each
PWM output may also be independently set.
8.2
Main Features
● 2 distinct programmable frequencies between 31.250 kHz and 8 MHz.
● Resolution: tCPU
8.3
Functional Description
The free-running 8-bit counter is fed by the CPU clock and increments on every rising edge of the
clock signal.
When a counter overflow occurs, the counter is automatically reloaded with the contents of the ARR
register.
Each PWMx output signal can be enabled independently using the corresponding OEx bit in the
PWM control register (PWMCR). When this bit is set, the corresponding I/O is configured as an
output push-pull alternate function.
PWM[3:0] all have the same frequency which is controlled by counter period A and the ARRA
register value.
fPWMA = fCOUNTERA / (256-ARRA)
PWM[5:4] all have the same frequency which is controlled by counter period B and the ARRB
register value.
fPWMB = fCOUNTERB / (256-ARRB)
When a counter overflow occurs, the PWMx pin level is toggled depending on the corresponding
OPx (output polarity) bit in the PWMCR register. When the counter reaches the value contained in
one of the Duty Cycle registers (DCRIx), the corresponding PWMx pin level is restored.
This DCRIx register can not be accessed directly, it is loaded from the Duty Cycle register (DCRx)
at each overflow of the counter. This double buffering method prevents glitch generation when
changing the duty cycle on the fly.
Note that the reload values will also affect the value and the resolution of the duty cycle of the PWM
output signal. To obtain a signal on a PWMx pin, the contents of the DCRx register must be greater
than or equal to the contents of the ARR register. The maximum available resolution for duty cycle
is 1/(256-ARR).
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