參數(shù)資料
型號(hào)： ST7FLCD1G9M1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO28
封裝： ROHS COMPLIANT, SO-28
文件頁(yè)數(shù)： 52/96頁(yè)
文件大?。?/td> 846K
代理商： ST7FLCD1G9M1
IC Single-Master Bus Interface
ST7FLCD1
10.6
Register Description
IC CONTROL REGISTER (I2CCR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits [7:6] = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral enable.
This bit is set and cleared by software.
0
Peripheral disabled
1
Master capability
Note:
When PE = 0, all the bits of the CR register and the SR register except the Stop bit are reset. All
outputs are released when PE = 0.
When PE = 1, the corresponding I/O pins are selected by hardware as alternate functions.
To enable the IC interface, write the CR register TWICE with PE = 1 as the first write only activates
the interface (only PE is set).
Bit 4 = Reserved. Forced to 0 by hardware
Bit 3 = START Generation of a Start condition. This bit is set and cleared by software. It is also
cleared by hardware when the interface is disabled (PE = 0) or when the Start condition is sent (with
interrupt generation if ITE = 1).
In Master mode:
0
No start generation
1
Repeated start generation
In Idle mode:
0
No start generation
1
Start generation when the bus is free
Bit 2 = ACK Acknowledge enable.
This bit is set and cleared by software. Cleared by hardware when the interface is disabled (PE = 0).
0
No acknowledge returned
1
Acknowledge returned after an address byte or a data byte is received
Table 21: IC Register Map
Addr.
(Hex.)
Reset
R/W
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
001Ch
00h
R/W
I2CCR
00
PE
0
START
ACK
STOP
ITE
001Dh
00h
Read only
I2CSR
EVF
AF
TRA
0
BTF
0
M/IDL
SB
001Eh
00h
R/W
I2CCCR
FM/SM
FILTOFF
CC[5:0]
001Fh
00h
R/W
I2CDR
DR7[:0]
765
432
10
00
PE
0
START
ACK
STOP
ITE
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