參數(shù)資料
型號: ST7FLCD1G9M1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO28
封裝: ROHS COMPLIANT, SO-28
文件頁數(shù): 72/96頁
文件大小: 846K
代理商: ST7FLCD1G9M1
Display Data Channel Interfaces (DDC)
ST7FLCD1
1
NACK or STOP condition met in Read mode.
Bit 4 = ENDCE End of Communication interrupt Enable.
This bit is set and cleared by software.
0
End of Communication interrupt disabled.
1
End of Communication interrupt enabled.
Bit 3 = EDF End of Download interrupt Flag.
This bit is set by hardware. An interrupt is generated if EDE = 1. It must be cleared by software.
0
Download not started or not completed yet.
1
Download completed. Last byte of data structure (relative address 7Fh or FFh) has been stored
or read in RAM.
In Read Mode: EDF is set upon reading the next byte after the internal address counter has rolled
over from 7Fh to 00h, or FFh to 80h.
In Write Mode: EDF is set when the last byte of data structure has been stored in RAM, and only if
writing to the RAM is enabled (bit WP = 0). if writing occurs but WP=1, EDF is not set.
Bit 2 = EDE End of Download interrupt Enable.
This bit is set and cleared by software.
0
End of Download interrupt disabled.
1
End of Download interrupt enabled.
Bit 1 = WP Write Protect.
This bit is set and cleared by software.
0
Enable writes to the RAM.
1
Disable DMA write transfers and protect the RAM content.
CPU writes to the RAM are not affected.
Bit 0 = DDC2BPE DDC2B Peripheral Enable.
This bit is set and cleared by software.
0
Release the SDA port pin and ignore SCL port pin. The other bits of the DCR are left un-
changed.
1
Enable the DDC Interface and respond to the DDC2B protocol.
Note:
When DDC2BPE = 1, all the bits of the DCR register are locked and cannot be changed. The
desired configuration therefore must be written in the DCR register with DDC2BPE = 0 and then set
the DDC2BPE bit in a second step.
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