參數(shù)資料
型號: ST7FLCD1G9M1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO28
封裝: ROHS COMPLIANT, SO-28
文件頁數(shù): 46/96頁
文件大小: 846K
代理商: ST7FLCD1G9M1
8-bit Analog-to-Digital Converter (ADC)
ST7FLCD1
Characteristics
The conversion is monotonic, the result never decreases or increases if the analog input does not
also drecrease or increase.
If the input voltage is greater than or equal to VDD (voltage reference high), the results are equal to
FFh (full scale) without overflow indication.
If the input voltage is less than or equal to VSS (voltage reference low), the results are equal to 00h.
The A/D converter is linear, the digital result of the conversion is given by the formula:
The conversion accuracy is described in Section 17: Electrical Characteristics.
When the A/D converter is continuously “ON”, the conversion time is 16 ADC clock cycles which
corresponds to 64 CPU clock cycles.
The internal circuitry is in auto-calibration during the conversion cycle. This process prevents offset
drifts. Still, calibration cycles are required at start-up or after any A/D converter re-start.
Procedure
Refer to the CSR and SR registers in Section 9.4: Register Description for the bit definitions.
At start-up, the A/D converter is OFF (ADON bit equal to ‘0’).
Prior to using the A/D converter, the analog input ports must be configured as inputs. Refer to
Section 7: I/O Ports. Using these pins as analog inputs does not affect the ability to read the port as
a logic input.
Then, the ADON bit must be set to 1. As internal AD circuitry starts calibration, it is mandatory to
respect the stabilizing time (several tens of milliseconds) prior to using A/D results.
In the CSR register, bits CH1 to CH0 select the analog channel to be converted (see Table 19).
These bits are set and cleared by software.
The A/D converter performs a continuous conversion of the selected channel.
When a conversion is complete, the COCO bit is set by hardware, but no interrupt is generated. The
result is written in the DR register.
Reading the DR result register resets the COCO bit.
Writing to the CSR register aborts the current conversion, the COCO bit is reset and a new
conversion is started.
Note:
Resetting the ADON bit disables the A/D converter. Thus, power consumption is reduced when no
conversions are needed.
The A/D converter is not affected by WAIT mode.
9.4
Register Description
Table 19: ADC Register Map
Address
Reset
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
000Ah
00h
R
ADCDR
AD[7:0]
000Bh
00h
R/W
ADCCSR
COCO
0
ADON
0
CH[1:0]
Digital result =
255 x Input Voltage
Supply Voltage
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