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參數(shù)資料
| 型號： | ST7FLCD1G9M1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | ROHS COMPLIANT, SO-28 |
| 文件頁數(shù)： | 48/96頁 |
| 文件大?。?/td> | 846K |
| 代理商： | ST7FLCD1G9M1 |
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IC Single-Master Bus Interface
ST7FLCD1
10
IC Single-Master Bus Interface
10.1
Introduction
The IC Bus Interface serves as an interface between the microcontroller and the serial IC bus. It
provides single-master functions, and controls all IC bus-specific sequencing, protocol and timing.
It supports Fast IC mode (400 kHz) and up to 800 kHz for certain applications.
10.2
Main Features
● Parallel / IC bus protocol converter
● Interrupt generation
● Standard IC mode/Fast IC mode (up to 800 kHz for certain applications)
● 7-bit Addressing
IC Single Master Mode
● End of byte transmission flag
● Transmitter /Receiver flag
● Clock generation
10.3
General Description
In addition to receiving and transmitting data, this interface converts data from serial to parallel
format and vice versa, using either an interrupt or a polled handshake. The interrupts are enabled or
disabled by software. The interface is connected to the IC bus by a data pin (SDAI) and by a clock
pin (SCLI). It can be connected both with a standard IC bus and a Fast IC bus. This selection is
made by software.
Mode Selection
The interface can operate in the two following modes:
1. Master transmitter/receiver,
2. Idle (default).
The interface automatically switches from Idle to Master mode after it generates a START condition
and from Master to Idle mode after it generates a STOP condition.
Communication Flow
The interface initiates a data transfer and generates the clock signal. A serial data transfer always
begins with a start condition and ends with a stop condition. Both start and stop conditions are
generated by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte following the start
condition is the address byte.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to Figure 28.
Acknowledge is enabled and disabled by software.
The speed of the IC interface is selected as Standard (0 to 100 kHz) and Fast IC (100 to 400 kHz)
and up to 800 kHz for certain applications.
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