參數(shù)資料
型號(hào)： ST7FLCD1G9M1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO28
封裝： ROHS COMPLIANT, SO-28
文件頁(yè)數(shù)： 69/96頁(yè)
文件大?。?/td> 846K
代理商： ST7FLCD1G9M1
ST7FLCD1
Display Data Channel Interfaces (DDC)
Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event occurs. It is cleared by software by reading the SR2
register in case of an error event or as described in Figure 39. It is also cleared by hardware when
the interface is disabled (PE = 0).
0
No event
1
One of the following events has occurred:
BTF = 1 (Byte received or transmitted)
ADSL = 1 (Either address matched in Slave mode when ACK = 1)
AF = 1 (No acknowledge received after byte transmission if ACK = 1)
STOPF = 1 (Stop condition detected in Slave mode)
BERR = 1 (Bus error, misplaced Start or Stop condition detected)
Bit 6 = Reserved. Forced to 0 by hardware.
Bit 5 = TRA Transmitter/Receiver.
When BTF is set, TRA = 1 if a data byte has been transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware after a Stop condition (STOPF = 1) is detected or when the
interface is disabled (PE = 0).
0
Data byte received (if BTF = 1)
1
Data byte transmitted
Bit 4 = BUSY Bus busy.
This bit is set by hardware on detection of a Start condition and cleared by hardware when a Stop
condition is detected. It indicates that a communication is in progress on the bus. This information is
still updated when the interface is disabled (PE = 0).
0
No communication on the bus
1
Communication ongoing on the bus
Bit 3 = BTF Byte transfer finished.
This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt
generation if ITE = 1. It is cleared by software by reading the SR1 register followed by a read or a
write to the DR register. It is also cleared by hardware when the interface is disabled (PE = 0).
Following a byte transmission, this bit is set after reception of the acknowledge clock pulse BTF is
cleared by reading the SR1 register followed by writing the next byte in the DR register.
Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK
= 1. BTF is cleared by reading SR1 register followed by reading the byte from DR register.
The SCL line is held low when BTF = 1.
0
Byte transfer not completed
1
Byte transfer succeeded
Bit 2 = ADSL Address matched (Slave mode). This bit is set by hardware as soon as the received
slave address matched with the OARx registers content or the DDC/CI address is recognized. An
interrupt is generated if ITE = 1. It is cleared by software by reading the SR1 register or by hardware
when the interface is disabled (PE = 0).
The SCL line is held low when ADSL = 1.
0
Address mismatched or not received
1
Received address matched
Bits [1:0] = Reserved. Forced to 0 by hardware.
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ST7FLI19BF1U6TR 功能描述:8位微控制器 -MCU 8-Bit MCU w/ Single Volt Flash RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST7FLI19BY1M3TR 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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