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| 型號： | ST7FLCD1G9M1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | ROHS COMPLIANT, SO-28 |
| 文件頁數(shù)： | 59/96頁 |
| 文件大小： | 846K |
| 代理商： | ST7FLCD1G9M1 |
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Display Data Channel Interfaces (DDC)
ST7FLCD1
11.3
Signal Description
11.3.1 Serial Data (SDA)
The SDA bidirectional pin is used to transfer data in and out of the device. An external pull-up
resistor must be connected to the SDA line. Its value depends on the load of the line and the
transfer rate.
11.3.2 Serial Clock (SCL)
The SCL input pin is used to synchronize all data in and out of the device when in IC bidirectional
mode. An external pull-up resistor must be connected to the SCL line. Its value depends on the load
of the line and the transfer rate.
Note:
When the DDC2B and DDC/CI Factory Interfaces are disabled (HWPE bit = 0 in the DCR register
and PE bit = 0 in the CR register), the SDA and SCL pins revert to being standard I/O pins.
11.4
DDC Standard
The DDC standard is divided into several data transfer protocols: DDC2B, DDC/CI and other slave
communication standards (HDCP, E-DDC, etc.).
For DDC2B, refer to the “VESA DDC Standard v3.0” specification. For DDC/CI refer to the “VESA
DDC Commands Interface v1.0”
DDC2B is a unidirectional channel from display to host. The host computer uses base-level IC
commands to read the EDID data from the display which is always in Slave mode.
DDC/CI is a bidirectional channel between the host computer and the display. The DDC/CI offers a
display control interface based on IC bus. Only the DDC2Bi interface is supported (and not the
DDC2B+ or DDC2AB interfaces).
11.4.1 DDC2B Interface
The DDC2B Interface acts as an I/O interface between a DDC bus and the MCU memory. In
addition to receiving and transmitting serial data, this interface directly transfers parallel data to and
from memory using a DMA engine, only halting CPU activity for 2 clock cycles during each byte
transfer.
The interface supports the following by hardware:
● DDC2B communication protocol
● write operations into RAM
● read operations from RAM
In DDC2B mode, it operates in IC Slave mode.
Device addresses A0h/A1h are recognized. EDID version 1 is used.
The Write and Read operations allow the EDID data to be downloaded during factory alignment (for
example).
Writing to the memory by the DMA engine is inhibited by the WP bit in the DCR register. A write of
the last data structure byte sets a flag and may be programmed to generate an interrupt request.
The Data address (sub-address) is either the second byte of write transfers or is pointed to by the
internal address counter which automatically increments after each byte transfer. The physical
address mapping of the data structure is fixed by hardware in a dedicated RAM area (see Table 24:
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