參數(shù)資料
型號： ST7FLCD1G9M1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO28
封裝： ROHS COMPLIANT, SO-28
文件頁數(shù)： 31/96頁
文件大?。?/td> 846K
代理商： ST7FLCD1G9M1
ST7FLCD1
I/O Ports
An alternate Input must first be configured in Input mode (DDR = 0). Alternate and I/O Input
configurations are identical without pull-up. The signal to be input in the peripheral is taken after the
TTL Schmitt trigger when available.
The I/O state is readable as in Input mode by addressing the corresponding I/O Data Register.
7.3
Port A
Each Port A bit can be defined as an Input line or as a Push-Pull. It can be also be used to output
the PWM outputs.
Outputs PA4 and PA5 may also be configured as high current (8 mA) push-pull outputs by means of
the MISCR register.
MISCELLANEOUS REGISTER (MISCR)
Read/Write
Reset value:00h
Bits [7:3] = Reserved. Forced by hardware to 0.
Bit 2 = PA5OVD Port A Bit 5 Overdrive
This bit is set and cleared by software. It is used only if Port A Bit 5 is set as an output (PADDR,
PWM5 or BUZOUT). It has no effect if set as an input.
0
2 mA Push-pull Output
1
8 mA Push-pull Output
Table 11: Port A Description
Port A
I / O
Alternate Function
Input1
1. Reset state.
Output
Signal
Condition
PA0
with Weak Pull-up
Push-pull
PWM0
OE0 = 1 (PWM)
PA1
with Weak Pull-up
Push-pull
PWM1
OE1 = 1 (PWM)
PA2
with Weak Pull-up
Push-pull
PWM2
OE2 = 1 (PWM)
PA3
with Weak Pull-up
Push-pull
PWM3
OE3 = 1 (PWM)
PA4
with Weak Pull-up
Push-pull
PWM4
OE4 = 1 (PWM)
PA5
with Weak Pull-up
Push-pull
PWM5
OE5 = 1 (PWM)
with Weak Pull-up
BUZOUT
BUZEN = 1 (Timer A)2
2. If both PWM5 and BUZOUT are enabled, BUZOUT has priority over PWM5.
PA6
with Weak Pull-up
Push-pull
External Interrupt ITA
see External Interrupt
Register Description
PA7
with Weak Pull-up
Push-pull
External Interrupt ITB
765
432
10
0
PA5OVD
PA4OVD
0
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