參數(shù)資料
型號： ST7FLCD1G9M1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO28
封裝： ROHS COMPLIANT, SO-28
文件頁數(shù)： 74/96頁
文件大?。?/td> 846K
代理商： ST7FLCD1G9M1
Watchdog Timer (WDG)
ST7FLCD1
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).
The application program must write in the CR register at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h
(see Table 25).
12.4
Lock-up Counter
An 8-bit counter starts after a reset or by writing to the CR register. It disables the writing of the CR
register during the next 256 cycles of CPU clock (typical value of 32 s at 8 MHz). If a writing order
takes place during this time, this 8-bit counter is reset but not the main watchdog downcounter (no
writing to the CR register occurs).
Thus after several too close writings of the CR register, the main downcounter reaches the reset
value and a reset occurs. If the CR register is normally refreshed every 32 s or more, write
commands are always enabled.
12.5
Interrupts
None.
12.6
Register Description
WDG CONTROL REGISTER (WDGCR)
Read/Write
Reset Value: 2 1111 (7Fh)
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0
Watchdog disabled
1
Watchdog enabled
Bits [6:0] = T[6:0] 7-bit Timer (MSB to LSB).
These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh
(T6 is cleared).
Table 25: Watchdog Timing (fCPU = 8 MHz)
CR Register Initial Value
WDG Timeout (ms)
Lock-up Timeout (s)
Maximum
FFh
400
32
Minimum
C0h
6.250
Table 26: Watchdog Register Map
Address
Reset
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
001Bh
7F
R/W
WDGCR
WDGA
T[6:0]
765
432
10
WDGA
T6
T5
T4
T3
T2
T1
T0
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