參數(shù)資料
型號(hào)： ST7FLCD1G9M1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO28
封裝： ROHS COMPLIANT, SO-28
文件頁(yè)數(shù)： 50/96頁(yè)
文件大小： 846K
代理商： ST7FLCD1G9M1
IC Single-Master Bus Interface
ST7FLCD1
10.4
Functional Description (Master Mode)
By default, the IC interface operates in Idle mode (M/IDL bit is cleared) except when it initiates a
transmit or receive sequence.
To switch from default Idle mode to Master mode a Start condition must be generated.
Setting the START bit causes the interface to switch to Master mode (M/IDL bit set) and generates
a Start condition.
Once the Start condition is sent, the EVF and SB bits are set by hardware and an interrupt is
generated if the ITE bit is set.
Then the master waits for a read of the SR register followed by a write in the DR register with the
Slave address byte, holding the SCL line low (EV1).
Then the slave address byte is sent to the SDA line via the internal shift register.
After completion of this transfer (and the reception of an acknowledge from the slave if the ACK bit
is set), the EVF bit is set by hardware and an interrupt is generated if the ITE bit is set.
Then the master waits for a read of the SR register followed by a write in the CR register (for
example set PE bit), holding the SCL line low (EV2).
Next the master must enter Receiver or Transmitter mode.
10.5
Transfer Sequencing
10.5.1 Master Receiver
Following the address transmission and after SR and CR registers have been accessed, the master
receives bytes from the SDA line into the DR register via the internal shift register. After each byte
the interface generates in sequence:
● an Acknowledge pulse if the ACK bit is set
● EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR register followed by a read of the DR register, holding
the SCL line low (EV3).
To close the communication, before reading the last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface automatically returns to Idle mode (M/IDL bit cleared).
Note:
In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must
be cleared just before reading the second last data byte.
10.5.2 Master Transmitter
Following the address transmission and after SR register has been read, the master sends bytes
from the DR register to the SDA line via the internal shift register.
The master waits for a read of the SR register followed by a write in the DR register, holding the
SCL line low (EV4).
When the acknowledge bit is received, the interface sets the EVF and BTF bits with an interrupt if
the ITE bit is set.
To close the communication, after writing the last byte to the DR register, set the STOP bit to
generate the Stop condition. The interface automatically returns to Idle mode (M/IDL bit cleared).
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