參數(shù)資料
型號： ST7FLCD1G9M1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO28
封裝： ROHS COMPLIANT, SO-28
文件頁數(shù)： 64/96頁
文件大?。?/td> 846K
代理商： ST7FLCD1G9M1
ST7FLCD1
Display Data Channel Interfaces (DDC)
● Acknowledge pulse is generated if the ACK bit is set.
● EVF and ADSL bits are set.
● An interrupt is generated if the ITE bit is set.
Then the interface waits for a read of the SR1 register, holding the SCL line low (see EV1 in
Section 11.6: Transfer Sequencing). Next, the DR register must be read to determine from the least
significant bit if the slave must enter Receiver or Transmitter mode.
Slave Receiver
Following the address reception and after SR1 register has been read, the slave receives bytes
from the SDA line into the DR register via the internal shift register. After each byte, the following
events occur in sequence:
● an Acknowledge pulse is generated if the ACK bit is set.
● the EVF and BTF bits are set.
● an interrupt is generated if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see EV2 in Section 11.6: Transfer Sequencing).
Slave Transmitter
Following the address reception and after SR1 register has been read, the slave sends bytes from
the DR register to the SDA line via the internal shift register.
The slave waits for a read of the SR1 register followed by a write in the DR register, holding the
SCL line low (see EV3 in Section 11.6: Transfer Sequencing).
When the acknowledge pulse is received:
● the EVF and BTF bits are set.
● an interrupt is generated if the ITE bit is set.
Closing Slave Communication
After the last data byte is transferred, a Stop Condition is generated by the master. The interface
detects this condition and in this case:
● the EVF and STOPF bits are set.
● an interrupt is generated if the ITE bit is set.
Then the interface waits for a read of the SR2 register (see EV4 in Section 11.6: Transfer
Error Cases
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and the
BERR bits are set and an interrupt is generated if the ITE bit is set.
If it is a Stop condition, then the interface discards the data, releases the lines and waits for another
Start condition. If it is a Start condition, then the interface discards the data and waits for the next
slave address on the bus.
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set and an interrupt
is generated if the ITE bit is set.
Note:
In both cases, the SCL line is not held low. However, the SDA line can remain low due to possible
‘0’ bits transmitted last. It is then necessary to release both lines by software.
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