參數資料
型號: ST7FLCD1G9M1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO28
封裝: ROHS COMPLIANT, SO-28
文件頁數: 65/96頁
文件大?。?/td> 846K
代理商: ST7FLCD1G9M1
Display Data Channel Interfaces (DDC)
ST7FLCD1
How to Release the SDA / SCL Lines
Set and subsequently clear the STOP bit when BTF is set. The SDA/SCL lines are released after
the transfer of the current byte.
Other Events
ADSL: Detection of a Start condition after an acknowledge time-slot. The state machine is reset
and starts a new process. The ADSL bit is set and an interrupt is generated if the ITE bit is set. The
SCL line is stretched low.
STOPF: Detection of a Stop condition after an acknowledge time-slot. The state machine is reset.
Then the STOPF flag is set and an interrupt is generated if the ITE bit is set.
11.6
Transfer Sequencing
Slave Receiver
Slave Transmitter
Legend:
S = Start, P = Stop, A = Acknowledge, NA = Non-acknowledge and EVx = Event (with interrupt if
ITE = 1)
EV1: EVF = 1, ADSL = 1, cleared by reading register SR1.
EV2: EVF = 1, BTF = 1, cleared by reading register SR1 followed by reading DR register.
EV3: EVF = 1, BTF = 1, cleared by reading register SR1 followed by writing DR register.
EV3-1: EVF = 1, AF = 1 and BTF = 1, AF is cleared by reading register SR2, BTF is cleared by
releasing the lines (write STOP = 1, STOP = 0 in register CR) or by writing to register DR (DR
= FFh).
Note:
If the lines are released by STOP = 1, STOP = 0, the subsequent EV4 is not seen.
EV4: EVF = 1, STOPF = 1, cleared by reading register SR2.
S
Address
A
Data1
A
Data2
A
.....
DataN
A
P
EV1
EV2
EV4
S Address
A
Data1
A
Data2
A
.....
DataN
NA
P
EV1
EV3
EV3-1
EV4
Figure 39: Event Flags and Interrupt Generation
BTF
ADSL
AF
STOPF
BERR
EVF
Interrupt
ITE
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