參數(shù)資料
型號： ST7FLCD1G9M1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO28
封裝： ROHS COMPLIANT, SO-28
文件頁數(shù)： 68/96頁
文件大?。?/td> 846K
代理商： ST7FLCD1G9M1
Display Data Channel Interfaces (DDC)
ST7FLCD1
Bit 5 = PE DDC/CI Peripheral enable.
This bit is set and cleared by software.
0
Peripheral disabled
1
Peripheral enabled
Note:
When PE = 0, all the bits of the CR, SR1 and SR2 registers are reset.
All outputs are released when PE = 0
When PE = 1, the corresponding I/O pins are selected by hardware as alternate functions.
To enable the IC interface, write the CR register TWICE with PE = 1 as the first write only activates
the interface (only PE is set).
Bit 4 = DDCCIEN DDC/CI address detection enabled.
This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled
(PE = 0). The 6Eh/6Fh DDC/CI address is acknowledged.
0
DDC/CI address detection disabled
1
DDC/CI address detection enabled
Bit 3 = Reserved. Forced to 0 by hardware.
Bit 2 = ACK Acknowledge enable.
This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled
(PE = 0).
0
No acknowledge returned
1
Acknowledge returned after an address byte or a data byte is received
Bit 1 = STOP Release IC bus.
This bit is set and cleared by software or when the interface is disabled (PE = 0).
Slave Mode:
0
Nothing
1
Release the SCL and SDA lines after the current byte transfer (BTF = 1). The STOP bit has to
be cleared by software.
Bit 0 = ITE Interrupt enable.
This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE
= 0).
0
Interrupt disabled
1
Interrupt enabled
Refer to Figure 39 for the relationship between the events and the interrupt.
SCL is held low when the BTF or ADSL is detected.
DDC STATUS REGISTER 1 (DDCSR1)
Read Only
Reset Value: 0000 0000 (00h)
765
432
10
EVF
0
TRA
BUSY
BTF
ADSL
0
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