參數(shù)資料
型號: ST72371
廠商: 意法半導體
英文描述: 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M))
中文描述: 8 - 16K的光碟/雙層/存儲器,512字節(jié)RAM,ADC和DAC的器(PWM),定時器,IIC和脊髓損傷(8位微控制器(8米)位MCU)
文件頁數(shù): 87/94頁
文件大小: 642K
代理商: ST72371
87/94
ST72371/ST72372
6.5.1 I2C CHARACTERISTICS
Notes:
1. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
2. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
I2C Electrical specifications
Parameter
Symbol
Unit
Standard mode I2C
Min
Fast mode I2C
Min
Max
Max
Hysteresis of Schmitt trigger inputs
Fixed input levels
V
DD
-related input levels
Pulse width of spikes which must be sup-
pressed by the input filter
V
HYS
V
N/A
N/A
N/A
N/A
0.2
0.05 V
DD
T
SP
ns
N/A
N/A
0 ns
50 ns
Output fall time from VIH min to VIL max with
a bus capacitance from 10 pF to 400 pF
with up to 3 mA sink current at VOL1
with up to 6 mA sink current at VOL2
T
OF
ns
N/A
250
N/A
20+0.1Cb
20+0.1Cb
250
250
Input current eachI/O pinwith aninput voltage
between 0.4V and 0.9 V
DD
max
Capacitance for each I/O pin
N/A = Not Applicable
Cb = Capacitance of one bus in pF
I
μ
A
- 10
10
-10
10
C
pF
10
10
I2C Bus Timings
Standard I2C
Min
Parameter
Fast I2C
Min
Symbol
Unit
Max
Max
Bus free time between a STOP and START con-
dition
Hold time START condition. After this period,
the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Capacitive load for each bus line
4.7
1.3
T
BUF
ms
4.0
0.6
T
HD:STA
μ
s
4.7
4.0
4.7
0
1)
250
1.3
0.6
0.6
0
1)
100
20+0.1Cb
20+0.1Cb
0.6
T
LOW
T
HIGH
T
SU:STA
T
HD:DAT
T
SU:DAT
TR
TF
T
SU:STO
Cb
μ
s
μ
s
μ
s
ns
ns
ns
ns
ns
pF
0.9
2)
1000
300
300
300
4.0
400
400
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