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參數(shù)資料
| 型號： | ST72371 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M)) |
| 中文描述： | 8 - 16K的光碟/雙層/存儲器，512字節(jié)RAM，ADC和DAC的器（PWM），定時器，IIC和脊髓損傷（8位微控制器（8米）位MCU） |
| 文件頁數(shù)： | 31/94頁 |
| 文件大?。?/td> | 642K |
| 代理商： | ST72371 |
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ST72371/ST72372
WATCHDOG TIMER
(Cont’d)
4.2.3 Functional Description
The counter value stored in the CR register (bits
T6:T0), is decremented every 49,152 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 become cleared), it initiates a
reset cycle pulling low the reset pin for typically
500ns.
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to stored in the
CR register must be between FFh and C0h (see
Table 1):
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
diate reset
– The T5:T0 bitscontain thenumber of increments
which represents the time delay before the
watchdog produces a reset.
Table 12. Watchdog Timing (f
CPU
= 8 MHz)
CR Register
initial value
Max
FFh
Min
C0h
Notes:
Following a reset, the watchdog is disa-
bled. Once activated it cannot be disabled, except
by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
4.2.4 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
Bit 7=
WDGA
Activation bit
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Bit 6:0 =
T[6:0]
7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
become cleared) if WDGA=1.
Table 13.WDG Register Map
WDG timeout period
(ms)
393.216
6.144
7
0
WDGA
T6
T5
T4
T3
T2
T1
T0
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
0C
Reset Value
CR
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
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