參數(shù)資料
型號(hào)： ST72371
廠商： 意法半導(dǎo)體
英文描述： 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M))
中文描述： 8 - 16K的光碟/雙層/存儲(chǔ)器，512字節(jié)RAM，ADC和DAC的器（PWM），定時(shí)器，IIC和脊髓損傷（8位微控制器（8米）位MCU）
文件頁(yè)數(shù)： 13/94頁(yè)
文件大?。?/td> 642K
代理商： ST72371
13/94
ST72371/ST72372
CENTRAL PROCESSING UNIT
(Cont’d)
Condition Code Register (CC)
Read/Write
Reset Value: 111x1010
The 8-bit Condition Code register contains the in-
terrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
These bits can be individually tested and/or con-
trolled by specific instructions.
Bit 4 =
H
Half carry
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
bit 3 =
I
Interrupt mask
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in-
structions.
Note:
Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware when you en-
ter it and reset by the IRETinstruction at the end of
the interrupt routine. If the I bit is cleared by soft-
ware in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.
Bit 2 =
N
Negative
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7
th
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMIand JRPL instruc-
tions.
Bit 1 =
Z
Zero
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 =
C
Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
7
0
1
1
1
H
I
N
Z
C
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