參數(shù)資料
型號(hào)： ST72371
廠商： 意法半導(dǎo)體
英文描述： 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M))
中文描述： 8 - 16K的光碟/雙層/存儲(chǔ)器，512字節(jié)RAM，ADC和DAC的器（PWM），定時(shí)器，IIC和脊髓損傷（8位微控制器（8米）位MCU）
文件頁(yè)數(shù)： 49/94頁(yè)
文件大?。?/td> 642K
代理商： ST72371
49/94
ST72371/ST72372
I C BUS INTERFACE
(Cont’d)
4.4.4 Functional Description
Refer to the CR, SR1 and SR2 registers inSection
0.1.5. for the bit definitions.
By default the I
2
C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
4.4.4.1 Slave Mode
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
Address not matched
: the interface ignores it
and waits for another Start condition.
Address matched
: the interface generates in se-
quence:
– Acknowledge pulse if the ACK bit is set.
– EVF and ADSL bitsare set with an interrupt if the
ITE bit is set.
Then the interface waits for a read of the SR1 reg-
ister,
holding the SCL line low
(see Figure 3
Transfer sequencing EV1).
Next, read the DR register to determine from the
least significant bit ifthe slave must enter Receiver
or Transmitter mode.
Slave Receiver
Following the address reception and after SR1 re-
gister has been read, the slave receives bytes
from the SDA line into theDR registervia the inter-
nal shift register. After each byte the interface ge-
nerates in sequence:
– Acknowledge pulse if the ACK bit is set
– EVF and BTF bits are set with an interrupt if the
ITE bit is set.
Then the interface waits for a read of the SR1 re-
gister followed by a read of the DR register,
hol-
ding the SCL line low
(see Figure 3 Transfer se-
quencing EV2).
Slave Transmitter
Following the address reception and after SR1
register has been read,the slave sends bytes from
the DR registertothe SDA lineviathe internal shift
register.
The slave waits for a read of the SR1 register fol-
lowed by a write in the DR register,
holding the
SCL line low
(see Figure 3 Transfer sequencing
EV3).
When the acknowledge pulse is received:
– The EVF and BTF bits are set by hardware with
an interrupt if the ITE bit is set.
Closing slave communication
After the last data byte is transferred a Stop Con-
dition is generated by the master. The interface
detects this condition and sets:
– EVF and STOPF bits with an interrupt if the ITE
bit is set.
Then the interface waits for a read of the SR2 re-
gister (see Figure 3 Transfer sequencing EV4).
Error Cases
–
BERR
: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
the BERR bits are set with an interrupt if the ITE
bit is set.
Ifit is a Stop then the interface discards the data,
released the lines and waits for another Start
condition.
If it is a Start then the interface discards the data
and waits for the next slave address on the bus.
–
AF
: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set with an inter-
rupt if the ITE bit is set.
Note
: In both cases, SCL line is not held low;
however, SDA line can remain low due to possible
0 bits transmitted last. It is then necessary to re-
lease both lines by software.
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while
BTF is set. The SDA/SCL lines are released after
the transfer of the current byte.
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