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參數(shù)資料
| 型號： | ST72371 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M)) |
| 中文描述： | 8 - 16K的光碟/雙層/存儲器，512字節(jié)RAM，ADC和DAC的器（PWM），定時器，IIC和脊髓損傷（8位微控制器（8米）位MCU） |
| 文件頁數(shù)： | 17/94頁 |
| 文件大?。?/td> | 642K |
| 代理商： | ST72371 |
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17/94
ST72371/ST72372
RESET
(Cont’d)
Table 6. List of sections affected by RESET, WAIT and HALT (Refer to 3.6 for Wait and Halt Modes)
Figure 11. Reset Timing Diagram
Note:
Refer to Electrical Characteristics for values of t
DDR
and t
OXOV
Section
RESET
WAIT
HALT
CPU clock running at 4 MHz
X
Timer Prescaler reset to zero
X
Timer Counter set to FFFCh
X
All Timer enable bits set to 0 (disabled)
X
Data Direction Registers set to 0 (as Inputs)
X
Set Stack Pointer to 01FFh
X
Force Internal Address Bus to restart vector FFFEh, FFFFh
X
Set Interrupt Mask Bit (I-Bit, CC) to 1 (Interrupt disable)
X
Set Interrupt Mask Bit (I-Bit, CC) to 0 (Interrupt enable)
X
X
Reset HALT latch
X
Reset WAIT latch
X
Disable Oscillator (for 4096 cycles)
X
X
Set Timer Clock to 0
X
X
Watchdog counter reset
X
Watchdog register reset
X
Port data registers reset
X
Other on-chip peripherals: registers reset
X
V
DD
OSCIN
f
CPU
FFFF
FFFE
PC
RESET
WATCHDOG RESET
t
DDR
t
OXOV
4096 CPU
CLOCK
CYCLES
DELAY
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