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| 型號： | ST72371 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M)) |
| 中文描述： | 8 - 16K的光碟/雙層/存儲器，512字節(jié)RAM，ADC和DAC的器（PWM），定時器，IIC和脊髓損傷（8位微控制器（8米）位MCU） |
| 文件頁數(shù)： | 47/94頁 |
| 文件大?。?/td> | 642K |
| 代理商： | ST72371 |
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ST72371/ST72372
4.4 I C BUS INTERFACE (I2C)
4.4.1 Introduction
The I
2
C Bus Interface serves as an interface be-
tween the microcontroller and the serial I
2
C bus. It
provides both multimaster and slave functions,
and controls all I
2
C bus-specific sequencing, pro-
tocol, arbitration and timing. It supports fast I C
mode (400kHz).
4.4.2 Main Features
– Parallel bus/I
2
C protocol converter
– Multi-Master capability
– Interrupt generation
– Standard I
2
C mode/Fast I
2
C mode
– 7-bit Addressing
I
I
2
C Slave Mode
– Start bit detection flag
– Detection of misplaced Start or Stop condition
– Transfer problem detection
– Address Matched detection
– Default Address detection
– End of byte transmission flag
– Transmitter/Receiver flag
– Stop bit Detection
I
I
2
C Master Mode
– I
2
C bus busy flag
– Arbitration lost flag
– End of byte transmission flag
– Transmitter/Receiver flag
– Clock generation
4.4.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
by software. The interface is connected to the I
2
C
bus by a data pin (SDAI) and by a clock pin (SCLI).
It can be connected both with a standard I
2
C bus
and a Fast I
2
C bus. This selection is made by soft-
ware.
Mode Selection
The interface can operate in the four following mo-
des:
– Slave transmitter/receiver
– Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP generation, this allows Multi-Master capabi-
lity.
Communication Flow
In Master mode, it initiates a data transfer and ge-
nerates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
In Slave mode, the interface is capable of recogni-
sing its own address (7-bit), and the General Call
address. The General Call address detection may
be enabled or disabled by software.
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte following the start condi-
tion is the address byte; it is always transmitted in
Master mode.
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer toFig-
ure 1.
Figure 1.I
2
C BUS Protocol
SCL
SDA
1
2
8
9
MSB
ACK
STOP
CONDITION
START
CONDITION
VR02119B
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