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參數(shù)資料
| 型號： | ST72371 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M)) |
| 中文描述： | 8 - 16K的光碟/雙層/存儲器，512字節(jié)RAM，ADC和DAC的器（PWM），定時器，IIC和脊髓損傷（8位微控制器（8米）位MCU） |
| 文件頁數(shù)： | 28/94頁 |
| 文件大?。?/td> | 642K |
| 代理商： | ST72371 |
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ST72371/ST72372
I/O PORTS
(Cont’d)
4.1.3 Register Description
DATA REGISTERS (DR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 =
D7-D0
Data Register 8 bits.
The behaviour of the DR register depends on the
selected input/output configuration. Writing the DR
register is always taken in account even if the pin
is configured as an input. Reading the DR register
returns either the DR register latch content (pin
configured as output) or the digital value applied to
the I/O pin (pin configured as input).
DATA DIRECTION REGISTERS (DDR)
Read/Write
Reset Value: 0000 0000 (00h) (input mode)
Bit 7:0 =
DD7-DD0
Data Direction Register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
OPTION REGISTER (OR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 =
AD[7:0]
Port B Digital/Analog Input Con-
figuration Bits
0: The pull-up is connected and pin configured as
digital input (reset condition)
1: The pull-up is disconnected and the pin is con-
figured as analog input.
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
7
0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
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