參數(shù)資料
型號(hào): ST72371
廠商: 意法半導(dǎo)體
英文描述: 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M))
中文描述: 8 - 16K的光碟/雙層/存儲(chǔ)器,512字節(jié)RAM,ADC和DAC的器(PWM),定時(shí)器,IIC和脊髓損傷(8位微控制器(8米)位MCU)
文件頁(yè)數(shù): 22/94頁(yè)
文件大?。?/td> 642K
代理商: ST72371
22/94
ST72371/ST72372
POWER SAVING MODES
(Cont’d)
3.4.4 Halt Mode
The Halt mode is the MCU lowest power con-
sumption mode. The Halt mode is entered by exe-
cuting the HALT instruction. The internal oscillator
is then turned off, causing allinternal processing to
be stopped, including the operation of the on-chip
peripherals. The Halt mode cannot be used when
the watchdog is enabled, if the HALT instruction is
executed while the watchdog system is enabled, a
watchdog reset is generated thus resetting the en-
tire MCU.
When entering Halt mode, the I bit in the CC Reg-
ister is cleared so as to enable External Interrupts.
If an interrupt occurs, the CPU becomes active.
The MCU can exit the Halt mode upon reception of
an interrupt or a reset. Refer to the Interrupt Map-
ping Table. The oscillator is then turned on and a
stabilization timeis provided before releasing CPU
operation. The stabilization timeis 4096 CPU clock
cycles.
After the start up delay, the CPU continues oper-
ation by servicing the interrupt which wakes itup or
by fetching the reset vector if a reset wakes it up.
Figure 14. HALT Flow Chart
N
N
EXTERNAL
INTERRUPT*
RESET
HALT INSTRUCTION
4096 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU CLOCK
I-BIT
OSCILLATOR
PERIPH. CLOCK
ON
ON
ON
SET
CPU CLOCK
I-BIT
OSCILLATOR
PERIPH. CLOCK
OFF
OFF
OFF
CLEARED
Y
Y
WDG
ENABLED
N
Y
RESET
WATCHDOG
* or some specific interrupts
Note:
Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
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