參數(shù)資料
型號(hào)： ST72371
廠商： 意法半導(dǎo)體
英文描述： 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M))
中文描述： 8 - 16K的光碟/雙層/存儲(chǔ)器，512字節(jié)RAM，ADC和DAC的器（PWM），定時(shí)器，IIC和脊髓損傷（8位微控制器（8米）位MCU）
文件頁(yè)數(shù)： 32/94頁(yè)
文件大?。?/td> 642K
代理商： ST72371
32/94
ST72371/ST72372
4.3 16-BIT TIMER
4.3.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture or generation of up to two out-
put waveforms (output compareand PWM).
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
4.3.2 Main Features
I
Programmable prescaler:f
CPU
divided by2,4or8.
I
Overflow status flag and maskable interrupt
I
External clock input (must be at least 4 times
slower than theCPUclockspeed) withthechoice
of active edge
I
Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
I
Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
I
Pulse width modulation mode (PWM)
I
One pulse mode
I
5 alternate functions on I/O ports*
The Block Diagram is shown inFigure 1.
*Note:
Some external pins are not available on all
devices. Refer to the device pin out description.
When reading an input signal which is not availa-
ble on an external pin, the value will always be ‘1’.
4.3.3 Functional Description
4.3.3.1 Counter
The principal block of the Programmable Timer is
a 16-bit free running increasing counter and its as-
sociated 16-bit registers:
Counter Registers
– Counter High Register (CHR) is the most sig-
nificant byte (MSB).
– Counter Low Register (CLR) is the least sig-
nificant byte (LSB).
Alternate Counter Registers
– Alternate Counter High Register (ACHR) is the
most significantbyte (MSB).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LSB).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (overflow
flag), (see note at the end of paragraph titled 16-bit
read sequence).
Writing in the CLRregister or ACLR register resets
the free running counter to the FFFCh value.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated inTable 1. The
value in the counter register
131.072, 262.144 or 524.288 internal processor
clock cycles depending on the CC1 and CC0 bits.
repeats
every
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