參數(shù)資料
型號: ST72371
廠商: 意法半導(dǎo)體
英文描述: 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M))
中文描述: 8 - 16K的光碟/雙層/存儲器,512字節(jié)RAM,ADC和DAC的器(PWM),定時器,IIC和脊髓損傷(8位微控制器(8米)位MCU)
文件頁數(shù): 55/94頁
文件大?。?/td> 642K
代理商: ST72371
55/94
ST72371/ST72372
I
2
C INTERFACE (Cont’d)
I
2
C CLOCK CONTROL REGISTER (CCR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7 =
FM/SM
Fast/Standard I
2
C mode.
This bit is set and cleared by software.It is not
cleared when the interface is disabled (PE=0).
0: Standard I
2
C mode
1: Fast I
2
C mode
Bit 6:0 =
CC6-CC0
7-bit clock divider.
These bits select the speed of the bus (F
SCL
) de-
pending on the I
2
C mode. They are not cleared
when the interface is disabled (PE=0).
– Standard mode (FM/SM=0): F
SCL
<= 100kHz
F
SCL
= f
CPU
/(2x([CC6..CC0]+2))
– Fast mode (FM/SM=1): F
SCL
> 100kHz
F
SCL
= f
CPU
/(3x([CC6..CC0]+2))
Note: The programmed F
SCL
assumes no load on
SCL and SDA lines.
I
2
C DATA REGISTER
(
DR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:0 =
D7-D0
8-bit Data Register.
These bits contains the byte to be received or
transmitted on the bus.
– Transmitter mode: Byte transmission start auto-
matically when the software writes in the DR reg-
ister.
– Receiver mode: the first data byte is received au-
tomatically in the DR register using the least sig-
nificant bit of the address.
Then, the next data bytes are received one by
one after reading the DR register.
I
2
C OWN ADDRESS REGISTER (OAR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:1 =
ADD7-ADD1
Interface address
These bits define the I
2
C bus address of the inter-
face. They are not cleared when the interface is
disabled (PE=0).
Bit 0 =
ADD0
Address direction bit.
This bit is don’t care, the interface acknowledges
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
Note: Address 01h is always ignored.
7
0
FM/SM
CC6
CC5
CC4
CC3
CC2
CC1
CC0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
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