參數(shù)資料
型號(hào): SM320F2812HFGM
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-BIT, 150 MHz, OTHER DSP, CQFP172
封裝: NCTB, CERAMIC, QFP-172
文件頁數(shù): 94/147頁
文件大?。?/td> 1721K
代理商: SM320F2812HFGM
Peripherals
50
December 2004
SGUS053
In the F2812 device, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 42.
INT1
to
INT12
INT14
C28x
TINT2
TINT0
PIE
CPU-TIMER 0
CPU-TIMER 2
(Reserved for TI
system functions)
INT13
TINT1
CPU-TIMER 1
(Reserved for TI
system functions)
XINT13
NOTES: A. The timer registers are connected to the Memory Bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 42. CPU-Timer Interrupts Signals and Output Signal (See Notes A and B)
The general operation of the timer is as follows: The 32-bit counter register “TIMH:TIM” is loaded with the value
in the period register “PRDH:PRD”. The counter register, decrements at the SYSCLKOUT rate of the C28x.
When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed
in Table 41 are used to configure the timers. For more information, see the TMS320x281x System Control
and Interrupts Reference Guide (literature number SPRU078).
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