參數(shù)資料
型號： SM320F2812HFGM
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號處理
英文描述： 16-BIT, 150 MHz, OTHER DSP, CQFP172
封裝： NCTB, CERAMIC, QFP-172
文件頁數(shù)： 27/147頁
文件大?。?/td> 1721K
代理商： SM320F2812HFGM
Electrical Specifications
122
December 2004
SGUS053
6.26
External Interface Ready-on-Write Timing With One External Wait State
Table 634. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
PARAMETER
MIN
MAX
UNIT
td(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low
1
ns
td(XCOHL-XZCSH)
Delay time, XCLKOUT high or low to zone chip-select inactive high
2
3
ns
td(XCOH-XA)
Delay time, XCLKOUT high to address valid
2
ns
td(XCOHL-XWEL)
Delay time, XCLKOUT high/low to XWE low
2
ns
td(XCOHL-XWEH)
Delay time, XCLKOUT high/low to XWE high
2
ns
td(XCOH-XRNWL)
Delay time, XCLKOUT high to XR/W low
1
ns
td(XCOHL-XRNWH)
Delay time, XCLKOUT high/low to XR/W high
2
1
ns
ten(XD)XWEL
Enable time, data bus driven from XWE low
0
ns
td(XWEL-XD)
Delay time, data valid after XWE active low
4
ns
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
ns
th(XD)XWE
Hold time, write data valid after XWE inactive high
TW2
ns
tdis(XD)XRNW
Data bus disabled after XR/W inactive high
4
ns
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
TW = trail period, write access (see Table 625)
Table 635. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)§
MIN
MAX
UNIT
tsu(XRDYsynchL)XCOHL
Setup time, XREADY (Synch) low before XCLKOUT high/low
15
ns
th(XRDYsynchL)
Hold time, XREADY (Synch) low
12
ns
te(XRDYsynchH)
Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
3
ns
tsu(XRDYsynchH)XCOHL
Setup time, XREADY (Synch) high before XCLKOUT high/low
15
ns
th(XRDYsynchH)XZCSH
Hold time, XREADY (Synch) held high after zone chip select high
0
ns
§ The first XREADY (Synch) sample occurs with respect to E in Figure 632:
E =(XWRLEAD + XWRACTIVE) tc(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found to be low, it will be sampled
again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D =(XWRLEAD + XWRACTIVE +n 1) tc(XTIM) tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 636. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
MIN
MAX
UNIT
tsu(XRDYasynchL)XCOHL
Setup time, XREADY (Asynch) low before XCLKOUT high/low
11
ns
th(XRDYasynchL)
Hold time, XREADY (Asynch) low
8
ns
te(XRDYasynchH)
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge
3
ns
tsu(XRDYasynchH)XCOHL
Setup time, XREADY (Asynch) high before XCLKOUT high/low
11
ns
th(XRDYasynchH)XZCSH
Hold time, XREADY (Asynch) held high after zone chip select high
0
ns
The first XREADY (Synch) sample occurs with respect to E in Figure 633:
E = (XWRLEAD + XWRACTIVE 2) tc(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is found to be low, it will be
sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE 3 + n) tc(XTIM) tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
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