參數(shù)資料
型號： SM320F2812HFGM
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號處理
英文描述： 16-BIT, 150 MHz, OTHER DSP, CQFP172
封裝： NCTB, CERAMIC, QFP-172
文件頁數(shù)： 44/147頁
文件大?。?/td> 1721K
代理商： SM320F2812HFGM
Electrical Specifications
137
December 2004
SGUS053
Table 645. McBSP Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
M1
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
2P
ns
M2
tw(CKRXH)
Pulse duration, CLKR/X high
CLKR/X int
D5§
D+5§
ns
M3
tw(CKRXL)
Pulse duration, CLKR/X low
CLKR/X int
C5§
C+5§
ns
M4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR int
0
4
ns
M4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR ext
3
27
ns
M5
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int
0
4
ns
M5
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX ext
3
27
ns
M6
tdis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance
CLKX int
8
ns
M6
tdis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance
following last data bit
CLKX ext
14
ns
Delay time, CLKX high to DX valid.
CLKX int
9
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
CLKX ext
28
M7
t
DXENA = 0
CLKX int
8
ns
M7
td(CKXH-DXV)
Delay time, CLKX high to DX valid
DXENA = 0
CLKX ext
14
ns
Only applies to first bit transmitted when in Data
DXENA = 1
CLKX int
P + 8
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY=01b or 10b) modes
DXENA = 1
CLKX ext
P + 14
DXENA = 0
CLKX int
0
M8
ten(CKXH-DX)
Enable time, CLKX high to DX driven
DXENA = 0
CLKX ext
6
ns
M8
ten(CKXH-DX)
Only applies to first bit transmitted when in Data
DXENA = 1
CLKX int
P
ns
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY=01b or 10b) modes
DXENA = 1
CLKX ext
P + 6
DXENA = 0
FSX int
8
M9
td(FXH-DXV)
Delay time, FSX high to DX valid
DXENA = 0
FSX ext
14
ns
M9
td(FXH-DXV)
Only applies to first bit transmitted when in Data
DXENA = 1
FSX int
P + 8
ns
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY=00b) mode.
DXENA = 1
FSX ext
P + 14
DXENA = 0
FSX int
0
M10
ten(FXH-DX)
Enable time, FSX high to DX driven
DXENA = 0
FSX ext
6
ns
M10
ten(FXH-DX)
Only applies to first bit transmitted when in Data
DXENA = 1
FSX int
P
ns
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY=00b) mode
DXENA = 1
FSX ext
P + 6
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
2P = 1/CLKG in ns.
§ C=CLKRX low pulse width = P
D=CLKRX high pulse width = P
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