參數(shù)資料
型號(hào)： SM320F2812HFGM
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-BIT, 150 MHz, OTHER DSP, CQFP172
封裝： NCTB, CERAMIC, QFP-172
文件頁數(shù)： 23/147頁
文件大?。?/td> 1721K
代理商： SM320F2812HFGM
Electrical Specifications
119
December 2004
SGUS053
6.25
External Interface Ready-on-Read Timing With One External Wait State
Table 630. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
PARAMETER
MIN
MAX
UNIT
td(XCOH-XZCSL)
Delay time, XCLKOUT high to zone chip-select active low
1
ns
td(XCOHL-XZCSH)
Delay time, XCLKOUT high/low to zone chip-select inactive high
2
3
ns
td(XCOH-XA)
Delay time, XCLKOUT high to address valid
2
ns
td(XCOHL-XRDL)
Delay time, XCLKOUT high/low to XRD active low
1
ns
td(XCOHL-XRDH
Delay time, XCLKOUT high/low to XRD inactive high
2
1
ns
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive high
ns
th(XA)XRD
Hold time, address valid after XRD inactive high
ns
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
Table 631. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
MAX
UNIT
ta(A)
Access time, read data from address valid
(LR + AR) 14
ns
ta(XRD)
Access time, read data valid from XRD active low
AR 12
ns
tsu(XD)XRD
Setup time, read data valid before XRD strobe inactive high
12
ns
th(XD)XRD
Hold time, read data valid after XRD inactive high
0
ns
LR = Lead period, read access. AR = Active period, read access. See Table 625.
Table 632. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)§
MIN
MAX
UNIT
tsu(XRDYsynchL)XCOHL
Setup time, XREADY (Synch) low before XCLKOUT high/low
15
ns
th(XRDYsynchL)
Hold time, XREADY (Synch) low
12
ns
te(XRDYsynchH)
Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
3
ns
tsu(XRDYsynchH)XCOHL
Setup time, XREADY (Synch) high before XCLKOUT high/low
15
ns
th(XRDYsynchH)XZCSH
Hold time, XREADY (Synch) held high after zone chip select high
0
ns
§ The first XREADY (Synch) sample occurs with respect to E in Figure 630:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found to be low, it will be sampled
again each tc(XTIM) until it is found to be high.
For each sample (n) the setup time (D) with respect to the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE +n 1) tc(XTIM) tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 633. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
MAX
UNIT
tsu(XRDYAsynchL)XCOHL
Setup time, XREADY (Asynch) low before XCLKOUT high/low
11
ns
th(XRDYAsynchL)
Hold time, XREADY (Asynch) low
8
ns
te(XRDYAsynchH)
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge
3
ns
tsu(XRDYAsynchH)XCOHL
Setup time, XREADY (Asynch) high before XCLKOUT high/low
11
ns
th(XRDYasynchH)XZCSH
Hold time, XREADY (Asynch) held high after zone chip select high
0
ns
The first XREADY (Asynch) sample occurs with respect to E in Figure 631:
E = (XRDLEAD + XRDACTIVE 2) tc(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is found to be low, it will be
sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE 3 +n) tc(XTIM) tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
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