參數(shù)資料
型號(hào): SM320F2812HFGM
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-BIT, 150 MHz, OTHER DSP, CQFP172
封裝: NCTB, CERAMIC, QFP-172
文件頁數(shù): 30/147頁
文件大?。?/td> 1721K
代理商: SM320F2812HFGM
Electrical Specifications
125
December 2004
SGUS053
6.27
XHOLD and XHOLDA
If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the
XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of
high-impedance mode.
On a reset (XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the bus
and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active low.
When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still execute
code from internal memory. If an access is made to the external interface, the CPU is stalled until the XHOLD
signal is removed.
An external DMA request, when granted, places the following signals in a high-impedance mode:
XA[18:0]
XZCS0AND1
XD[15:0]
XZCS2
XWE, XRD
XZCS6AND7
XR/W
All other signals not listed in this group remain in their default or functional operational modes during these
signal events. Detailed timing diagram will be released in a future revision of this data sheet.
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