參數(shù)資料
型號: SM320F2812HFGM
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 150 MHz, OTHER DSP, CQFP172
封裝: NCTB, CERAMIC, QFP-172
文件頁數(shù): 74/147頁
文件大?。?/td> 1721K
代理商: SM320F2812HFGM
Functional Overview
32
December 2004
SGUS053
3.2.16
Peripheral Frames 0, 1, 2 (PFn)
The F281x segregates peripherals into three sections. The mapping of peripherals is as follows:
PF0:
XINTF:
External Interface Configuration Registers (2812 only)
PIE:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash:
Flash Control, Programming, Erase, Verify Registers
Timers:
CPU-Timers 0, 1, 2 Registers
CSM:
Code Security Module KEY Registers
PF1:
eCAN:
eCAN Mailbox and Control Registers
PF2:
SYS:
System Control Registers
GPIO:
GPIO Mux Configuration and Control Registers
EV:
Event Manager (EVA/EVB) Control Registers
McBSP:
McBSP Control and TX/RX Registers
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
SPI:
Serial Peripheral Interface (SPI) Control and RX/TX Registers
ADC:
12-Bit ADC Registers
3.2.17
General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This enables the user
to use a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are configured
as inputs. The user can then individually program each pin for GPIO mode or Peripheral Signal mode. For
specific inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise
glitches.
3.2.18
32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling.
The timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero.
The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter
reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for Real-Time
OS (RTOS)/BIOS applications. CPU-Timer 1 is also reserved for TI system functions. CPU-Timer 2 is
connected to INT14 of the CPU. CPU-Timer 1 can be connected to INT13 of the CPU. CPU-Timer 0 is for
general use and is connected to the PIE block.
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