參數(shù)資料
型號： SM320F2812HFGM
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號處理
英文描述： 16-BIT, 150 MHz, OTHER DSP, CQFP172
封裝： NCTB, CERAMIC, QFP-172
文件頁數(shù)： 102/147頁
文件大?。?/td> 1721K
代理商： SM320F2812HFGM
Peripherals
58
December 2004
SGUS053
Result Registers
EVB
S/W
ADCSOC
EVA
S/W
Sequencer 2
Sequencer 1
SOC
ADC Control Registers
70B7h
70B0h
70AFh
70A8h
Result Reg 15
Result Reg 8
Result Reg 7
Result Reg 1
Result Reg 0
Module
ADC
12-Bit
Analog
MUX
ADCINA0
ADCINA7
ADCINB0
ADCINB7
System
Control Block
High-Speed
Prescaler
HSPCLK
ADCENCLK
C28x
SYSCLKOUT
S/H
Figure 44. Block Diagram of the F2812 ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible,
traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize
switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation
techniques must be used to isolate the ADC module power pins (VDDA1/VDDA2, AVDDREFBG) from the digital
supply. Figure 45 shows the ADC pin connections for the F2812 device.
Notes:
1.
The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is
controlled by the high-speed peripheral clock (HSPCLK).
2.
The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows:
ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the clock to the register will
still function. This is necessary to make sure all registers and modes go into their default reset state. The
analog module will however be in a low-power inactive state. As soon as reset goes high, then the clock to
the registers will be disabled. When the user sets the ADCENCLK signal high, then the clocks to the
registers will be enabled and the analog module will be enabled. There will be a certain time delay (ms
range) before the ADC is stable and can be used.
HALT: This signal only affects the analog module. It does not affect the registers. If low, the ADC module is
powered. If high, the ADC module goes into low-power mode. The HALT mode will stop the clock to the
CPU, which will stop the HSPCLK. Therefore the ADC register logic will be turned off indirectly.
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