參數(shù)資料
型號(hào)： SM320F2812HFGM
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-BIT, 150 MHz, OTHER DSP, CQFP172
封裝： NCTB, CERAMIC, QFP-172
文件頁數(shù)： 3/147頁
文件大?。?/td> 1721K
代理商： SM320F2812HFGM
Electrical Specifications
100
December 2004
SGUS053
Table 612. HALT Mode Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
td(IDLE-XCOH)
Delay time, IDLE instruction executed to XCLKOUT high
32 * tc(SCO)
45 *tc(SCO)
Cycles
tw(WAKE-XNMI)
Pulse duration, XNMI wakeup signal
2 * tc(CI)
Cycles
tw(WAKE-XRS)
Pulse duration, XRS wakeup signal
8 * tc(CI)
Cycles
tp
PLL lock-up time
131 072 * tc(CI) Cycles
Delay time, PLL lock to program execution resume
td(wake)
Wake-up from flash
Flash module in sleep state
1125*tc(SCO)
Cycles
Wake-up from SARAM
35*tc(SCO)
Cycles
XCLKOUT = SYSCLKOUT
NOTES: A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned off and the
CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. Clocks to the device are turned off and the internal oscillator and PLL are shut down. The device is now in HALT mode and
consumes absolute minimum power.
D. When XNMI is driven active (negative edge triggered shown , as an example), the oscillator is turned on; but the PLL is not
activated.
E. When XNMI is deactivated, it initiates the PLL lock sequence, which takes 131,072 X1/XCLKIN cycles.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now
exited.
G. Normal operation resumes.
td(IDLEXCOH)
32 SYSCLKOUT Cycles
X1/XCLKIN
XCLKOUT
HALT
Wakeup Latency
Flushing Pipeline
td(INT)
A
B
C
D
Device
Status
E
G
F
PLL Lockup Time
XNMI
Normal
Execution
tw(WAKEXNMI)
tp
Oscillator Start-up Time
Figure 614. HALT Wakeup Using XNMI
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