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參數(shù)資料
| 型號(hào)： | SAA7392 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Channel encoder/decoder CDR60(通道編碼器/譯碼器) |
| 中文描述： | 信道編碼器/解碼器CDR60（通道編碼器/譯碼器） |
| 文件頁(yè)數(shù)： | 55/76頁(yè) |
| 文件大?。?/td> | 246K |
| 代理商： | SAA7392 |
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2000 Mar 21
55
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.16.1
EFM C
LOCK
C
ONFIGURATION
R
EGISTER
1 (EFMC
LOCK
C
ONF
1)
Table 120
EFM Clock Configuration Register 1 (address 34H) - WRITE
Table 121
Description of EFMClockConf1 bits
Table 122
Selection of PLL bandwidth
Table 123
Selection of analog PLL output divisor
7
6
5
4
3
2
1
0
DPLLBW.2
DPLLBW.1
DPLLBW.0
Bypass
Div.2
Div.1
Div.0
BIT
SYMBOL
DESCRIPTION
7
6
5
4
DPLLBW.2
DPLLBW.1
DPLLBW.0
Bypass
These 3 bits select the digital PLL bandwidth; see Table 122.
When Bypass = 0, then bypass is off. When Bypass = 1, then PLL is bypassed and the
XEFM clock is derived from the system clock.
These 3 bits select the analog PLL output divisor; see Table 123.
3
2
1
0
Div.2
Div.1
Div.0
This bit is reserved.
DPLLBW.2
DPLLBW.1
DPLLBW.0
PLL BANDWIDTH
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Digital PLL bandwidth is 400 Hz.
Digital PLL bandwidth is 200 Hz.
Digital PLL bandwidth is 100 Hz.
Digital PLL bandwidth is 50 Hz.
Digital PLL bandwidth is 25 Hz.
Div.2
Div.1
Div.0
PLL DIVISOR
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Analog PLL output is divided by 1 (XEFM_2 output is not available).
Analog PLL output is divided by 2.
Analog PLL output is divided by 3 (XEFM_2 output is not available).
Analog PLL output is divided by 4.
Analog PLL output is divided by 6.
Analog PLL output is divided by 8.
Analog PLL output is divided by 12.
Analog PLL output is divided by 16.
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