參數(shù)資料
型號: SAA7392
廠商: NXP Semiconductors N.V.
英文描述: Channel encoder/decoder CDR60(通道編碼器/譯碼器)
中文描述: 信道編碼器/解碼器CDR60(通道編碼器/譯碼器)
文件頁數(shù): 40/76頁
文件大?。?/td> 246K
代理商: SAA7392
2000 Mar 21
40
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.10.1
M
OTOR
C
ONTROL
R
EGISTER
1 (M
OTOR
1)
The frequency/tacho set-point (i.e. the target PLL or tacho frequency) is calculated as follows:
Note that: (PLL frequency
frequency set-point) must be less than 1.33
×
ADC clock.
Table 70
Motor Control Register 1 (address 0CH) - WRITE
7.10.2
M
OTOR
C
ONTROL
R
EGISTER
2 (M
OTOR
2)
Table 71
Motor Control Register 2 (address 0DH) - WRITE
Table 72
Description of Motor2 bits
Table 73
Selection of coefficient G
7
6
5
4
3
2
1
0
MFS.7
MFS.6
MFS.5
MFS.4
MFS.3
MFS.2
MFS.1
MFS.0
7
6
5
4
3
2
1
0
G.2
G.1
G.0
Ki.1
Ki.0
Kf.2
Kf.1
Kf.0
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
G.2
G.1
G.0
Ki.1
Ki.0
These 3 bits select coefficient G; see Table 73.
These 2 bits select coefficient K
i
; see Table 74.
In order to set the integrator bandwidth low enough at high system clock speeds, an
extra divider for K
i
has been added. This is set by writing to register Motor7. The
resulting K
i(tot)
is then the K
i
set by Motor2 multiplied by the K
i’
set by Motor7.
These 3 bits select coefficient K
f
; see Table 75.
2
1
0
Kf.2
Kf.1
Kf.0
G.2
G.1
G.0
COEFFICIENT G
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8.36
10.4
16.7
20.9
33.4
41.8
66.9
83.6
Frequency set-point
1
256
MFS<7:0>
2.667
×
ADC clock
×
=
PLL frequency
128
PLLFreqR<7:0>
ADC clock
×
=
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