參數(shù)資料
型號(hào)： SAA7392
廠商： NXP Semiconductors N.V.
英文描述： Channel encoder/decoder CDR60(通道編碼器/譯碼器)
中文描述： 信道編碼器/解碼器CDR60（通道編碼器/譯碼器）
文件頁數(shù)： 23/76頁
文件大?。?/td> 246K
代理商： SAA7392
2000 Mar 21
23
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
Table 28
Description of PLLock bits for read operation
7.5.4
PLL B
ANDWIDTH
S
ELECT
R
EGISTER
(PLLS
ET
)
The function of this register is dependent upon whether its being read or written. The function for the write operation is
described in Tables 29 to 34. Note the measurement conditions are: system clock = 2.15 MHz, bit clock = 4.3 MHz,
bandwidth is proportional to the system clock.
When read this register returns the 8-bit PLL asymmetry value, see Table 29.
Table 29
PLL Bandwidth Select Register (address 01H) - WRITE/READ
Table 30
Description of PLLSet bits for write operation
Table 31
Selection of Slicer bandwidth
Table 32
Selection of integrator crossover frequency
BIT
SYMBOL
DESCRIPTION
7 to 0
PLLFreq<7:0> This register holds the 8 MSBs of the PLL frequency counter. The PLL frequency is
calculated as shown below:
7
6
5
4
3
2
1
0
SliceBW.1
PLLAsym.7
SliceBW.0
PLLAsym.6
IntegF0.1
PLLAsym.5
IntegF0.0
PLLAsym.4
PLLBWF1.1
PLLAsym.3
PLLBWF1.0
PLLAsym.2
LPBWF2.1
PLLAsym.1
LPBWF2.0
PLLAsym.0
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
SliceBW.1
SliceBW.0
IntegF0.1
IntegF0.0
PLLBWF1.1
PLLBWF1.0
LPBWF2.1
LPBWF2.0
These 2 bits select the Slicer bandwidth; see Table 31.
These 2 bits select the integrator crossover frequency; see Table 32.
These 2 bits select the PLL bandwidth; see Table 33.
These 2 bits select the low-pass bandwidth; see Table 34.
SliceBW.1
SliceBW.0
SLICER BANDWIDTH
0
0
1
1
0
1
0
1
12 Hz
50 Hz
200 Hz
This value is reserved.
IntegFO.1
IntegFO.0
INTEGRATOR CROSSOVER FREQUENCY
0
0
1
1
0
1
0
1
3780 Hz
1890 Hz
945 Hz
This value is reserved.
f
PLL
(Hz)
-PLLFreq<7:0>
ADC clock (Hz)
128
×
(
)
=
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