參數(shù)資料
型號(hào): SAA7392
廠(chǎng)商: NXP Semiconductors N.V.
英文描述: Channel encoder/decoder CDR60(通道編碼器/譯碼器)
中文描述: 信道編碼器/解碼器CDR60(通道編碼器/譯碼器)
文件頁(yè)數(shù): 13/76頁(yè)
文件大?。?/td> 246K
代理商: SAA7392
2000 Mar 21
13
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.2.1
I
NTERRUPT PIN
The interrupt pin (INT) is the AND-OR-INVERT of the Status and Interrupt Enable Registers, i.e. INT will become active
when corresponding bits are set at the same time in the Status and Interrupt Enable Registers.
7.2.2
T
HE
S
EMAPHORE
R
EGISTERS
(S
EMA
1, S
EMA
2
AND SEMA
3)
The Semaphore Registers are intended for inter-microprocessor communications. For example, microcontroller 1 can
write data to microcontroller 2 via Sema1 and microcontroller 2 can write data to microcontroller 1 via Sema2. The Status
Register of the SAA7392 offers a mechanism so that both microcontrollers can see when new data has been written and
when it has been read by looking at the contents of the Semaphore Registers. Version M3 of the CDR60 can be identified
by writing and reading register Sema3. In version M3, bit 1 of Sema3 is always read as logic 0, whereas in other CDR60
versions this bit reads the same value as what was written to it before.
7.2.2.1
Semaphore Register 1 (Sema1)
Table 4
Semaphore Register 1 (address 08H) - READ/WRITE
7.2.2.2
Semaphore Register 2 (Sema2)
Table 5
Semaphore Register 2 (address 09H) - READ/WRITE
7.2.2.3
Semaphore Register 3 (Sema3)
Table 6
Semaphore Register 3 (address 0AH) - READ/WRITE
7.2.3
S
TATUS
R
EGISTER
(S
TATUS
)
Table 7
Status Register (address 0BH) - READ
Table 8
Description of Status bits
7
6
5
4
3
2
1
0
Sema1.7
Sema1.6
Sema1.5
Sema1.4
Sema1.3
Sema1.2
Sema1.1
Sema1.0
7
6
5
4
3
2
1
0
Sema2.7
Sema2.6
Sema2.5
Sema2.4
Sema2.3
Sema2.2
Sema2.1
Sema2.0
7
6
5
4
3
2
1
0
Sema3.7
Sema3.6
Sema3.5
Sema3.4
Sema3.3
Sema3.2
Sema3.1
Sema3.0
7
6
5
4
3
2
1
0
Sema1
Sema2
Sema3
LockIn
HeaderVal
MotorOverflow
FIFOOv
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
Sema1
Sema2
Sema3
LockIn
HeaderVal
MotorOverflow If MotorOverflow = 1, then a motor overflow is occurring (not latched).
FIFOOv
If FIFOOv = 1, then the FIFO has overflowed.
This bit is reserved.
If Sema1 = 1, change in register Sema1 has been detected. Reset if register Sema1 read.
If Sema2 = 1, change in register Sema2 has been detected. Reset if register Sema2 read.
If Sema3 = 1, change in register Sema3 has been detected. Reset if register Sema3 read.
If LockIn = 1, then channel data PLL in lock (not latched).
HeaderVal is set when new header/subcode is available; reset on reading SubReadEnd.
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