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參數(shù)資料
| 型號： | SAA7392 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Channel encoder/decoder CDR60(通道編碼器/譯碼器) |
| 中文描述： | 信道編碼器/解碼器CDR60（通道編碼器/譯碼器） |
| 文件頁數(shù)： | 29/76頁 |
| 文件大?。?/td> | 246K |
| 代理商： | SAA7392 |
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2000 Mar 21
29
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.6.3
D
ECODER
M
ODE
S
ELECT
R
EGISTER
(D
ECO
M
ODE
)
Table 50
Decoder Mode Select Register (address 13H) - WRITE
Table 51
Description of DecoMode bits
Table 52
Selection of Decoder mode
7.6.4
F
RAME ERROR STATUS REGISTERS
(C1BLER
AND
C2BLER)
These two registers are non-buffered counters. Each time a C1 frame with errors is found the register C1BLER is
incremented. In the same way C2BLER increments on all C2 frames with errors. When the value of either register
reaches 255, it will hold. When read, the register value is reset.
7.6.4.1
C1 Block Error Register (C1BLER)
Table 53
C1 Block Error Register (address 39H) - READ
7.6.4.2
C2 Block Error Register (C2BLER)
Table 54
C2 Block Error Register (address 3AH) - READ
7
6
5
4
3
2
1
0
Mode.6
Mode.5
Mode.4
Mode.3
Mode.2
Mode.1
Mode.0
LWCon
BIT
SYMBOL
DESCRIPTION
7 to 1
0
Mode<6:0>
LWCon
These 7 bits select the Decoder mode; see Table 52.
When a logic 0, LaserOn and WriteOn2 signals operate normally. When a logic 1,
LaserOn and WriteOn2 signals are reset.
MODE
DECODER MODE
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
Flush mode.
Deinterleaver table is emptied and all data is discarded.
Normal play.
Uses the Quad-pass error correction mode used for disc speeds up
to 75% of maximum defined by ADCCLK. Note the data integrity should be
checked using the CRC as the FLAG pin is not fully defined in this mode.
Fast play.
Used for audio play or fast CDROM mode (25 to 100% of maximum
defined by ADCCLK), this reduces the error correction performance, but also
halves the throughput time of error corrector (only dual pass error correction
algorithm used).
Hold mode.
Data into output FIFO is stopped (header/subheader decoding
remains operative).
Encode mode.
All other combinations reserved.
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
X
1
X
0
X
1
X
0
X
1
X
0
X
7
6
5
4
3
2
1
0
C1BLER.7
C1BLER.6
C1BLER.5
C1BLER.4
C1BLER.3
C1BLER.2
C1BLER.1
C1BLER.0
7
6
5
4
3
2
1
0
C2BLER.7
C2BLER.6
C2BLER.5
C2BLER.4
C2BLER.3
C2BLER.2
C2BLER.1
C2BLER.0
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