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參數(shù)資料
| 型號(hào)： | SAA7392 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Channel encoder/decoder CDR60(通道編碼器/譯碼器) |
| 中文描述： | 信道編碼器/解碼器CDR60（通道編碼器/譯碼器） |
| 文件頁數(shù)： | 14/76頁 |
| 文件大小： | 246K |
| 代理商： | SAA7392 |
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2000 Mar 21
14
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.2.4
I
NTERRUPT
E
NABLE
R
EGISTER
(I
NT
E
N
)
Table 9
Interrupt Enable Register (address 0BH) - WRITE
Table 10
Description of IntEn bits
7.2.5
S
TATUS
R
EGISTER
2 (S
TATUS
2)
Table 11
Status Register 2 (address 20H) - READ/WRITE
Table 12
Description of Status2 bits
7
6
5
4
3
2
1
0
Sema1En
Sema2En
Sema3En
LockInEn
HeaderValen MotorOverflowEn
FIFOOvEn
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
Sema1En
Sema2En
Sema3En
LockInEn
HeaderValEn
MotorOverflowEn
FIFOOvEn
If Sema1En = 1, then Semaphore Register 1 interrupt is enabled.
If Sema2En = 1, then Semaphore Register 2 interrupt is enabled.
If Sema3En = 1, then Semaphore Register 3 interrupt is enabled.
If LockinEn = 1, then channel data PLL in lock interrupt is enabled.
If HeaderValEn = 1, then new header/subcode available interrupt is enabled.
If MotorOverflowEn = 1, then motor overflow interrupt is enabled.
If FIFOOvEn = 1, then FIFO overflow interrupt is enabled.
This bit is reserved.
7
6
5
4
3
2
1
0
BankSwitch
SyncError
DataNotValid
QSync
ATIPSync
LaserOn
LaserOff
XErrorLarge
BIT
SYMBOL
DESCRIPTION
7
BankSwitch
When set a ‘Bank switch’ in the subcode insert block has occurred; reset when a logic 1
is written to this bit.
When set synchronisation with PLUM on subcode transfer has failed; reset when a
logic 1 is written to this bit.
When set an under-run on subcode transfer with PLUM has occurred; reset when a
logic 1 is written to this bit.
When set a Q-channel subcode sync has been written to disc; reset when a logic 1 is
written to this bit.
When set sync has been found in the ATIP channel; reset when a logic 1 is written to
this bit.
When set a rising edge of the internal LaserOn signal has occurred; reset when a
logic 1 is written to this bit.
When set a falling edge of the internal LaserOn signal has occurred; reset when a
logic 1 is written to this bit.
When set the offset between QSync and ATIPSync is more than 2 EFM frames different
from the programmed value.
6
SyncError
5
DataNotValid
4
QSync
3
ATIPSync
2
LaserOn
1
LaserOff
0
XErrorLarge
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