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參數(shù)資料
| 型號(hào)： | SAA7392 |
| 廠(chǎng)商： | NXP Semiconductors N.V. |
| 英文描述： | Channel encoder/decoder CDR60(通道編碼器/譯碼器) |
| 中文描述： | 信道編碼器/解碼器CDR60（通道編碼器/譯碼器） |
| 文件頁(yè)數(shù)： | 41/76頁(yè) |
| 文件大?。?/td> | 246K |
| 代理商： | SAA7392 |
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2000 Mar 21
41
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
Table 74
Selection of coefficient K
i
Table 75
Selection of the coefficient K
f
7.10.3
M
OTOR
C
ONTROL
R
EGISTER
7 (M
OTOR
7)
Table 76
Motor Control Register 7 (address 1DH) - WRITE
Table 77
Description of Motor7 bits
Ki.1
Ki.0
COEFFICIENT K
i
0
0
1
1
0
1
0
1
3.1
×
10
5
6.1
×
10
5
1.2
×
10
4
2.4
×
10
4
Kf.2
Kf.1
Kf.0
COEFFICIENT K
f
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
reserved
3.7
×
10
9
7.5
×
10
9
1.5
×
10
8
3.0
×
10
8
6.0
×
10
8
1.2
×
10
7
2.4
×
10
7
7
6
5
4
3
2
1
0
PhErSrc
Kf’.2
Kf’.1
Kf’.0
Ki’.2
Ki’.1
Ki’.0
BIT
SYMBOL
DESCRIPTION
7
PhErSrc
If PhErSrc = 0, then the phase error source is FIFOFil. If PhErSrc = 1, then the phase
error source is XError.
This bit is reserved.
These 3 bits select the value of the K
f’
coefficient; see Table 78.
6
5
4
3
Kf’.2
Kf’.1
Kf’.0
K
f’
operates by sampling the input. For example, for K
f’
= 1, every sample of the input is
passed through to a following integrator circuit, for a K
f’
of 0.5 every 2nd sample is
passed through, for a K
f’
of 0.25 every 4th sample is passed through, and so on.
For a DC input signal, K
f
×
K
f’
should always give the same result. If however, the input
is varying sufficiently quickly, the K
f
×
K
f’
combinations with the same product will not
always give the same result, especially for low values of K
f’
, where the sampling in the
extreme becomes 1 out of every 128 samples. (The input samples to the block that
performs the K
f’
multiplication occur at a rate of 1 sample every 24 system clock
periods.)
These 3 bits select the value of the K
i’
coefficient; see Table 78.
2
1
0
Ki’.2
Ki’.1
Ki’.0
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