
2
1
P
P
C
S
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7.2
Register map
Table 3
Register map
ADDRESS
(HEX)
REGISTER NAME
TYPE
FUNCTION
BLOCK
RESPONSIBLE
00
PLL Lock Select Register (PLLLock)
Write
Read
Write
Read
Write
Read
Write
Read
Write
Write
Write
Write
Write/Read
PLL lock select
8-bit PLL frequency
PLL bandwidth select
8-bit asymmetry signal
PLL frequency preset
8-bit jitter signal
PLL equalizer preset
Observe internal lock flags
PLL lock aid 2 preset
I
2
S output 1
I
2
S output 2
I
2
S output 3
Inter-microprocessor
communication
Inter-microprocessor
communication
Inter-microprocessor
communication
Enable interrupts
Interrupt status
Frequency set-point
8-bit slicer compensation
value
Motor coefficient preset
Opening of eye pattern
Motor integrator preset
Read back of motor frequency motor/tacho
Motor control
Motor integrator value
Motor integrator value
bit detector
bit detector
bit detector
bit detector
bit detector
bit detector
bit detector
bit detector
bit detector
serial out
serial out
serial out
sub-CPU
01
PLL Bandwidth Select Register (PLLSet)
02
PLL Frequency Preset Register (PLLFreq)
03
PLL Equalizer Preset Register (PLLEqu)
04
05
06
07
08
PLL Lock Aid2 Preset Register (PLLFMeas)
I
2
S Output Register 1 (Output1)
I
2
S Output Register 2 (Output2)
I
2
S Output Register 3 (Output3)
Semaphore Register 1 (Sema1)
09
Semaphore Register 2 (Sema2)
Write/Read
sub-CPU
0A
Semaphore Register 3 (Sema3)
Write/Read
sub-CPU
0B
0B
0C
Interrupt Enable Register (IntEn)
Status Register (Status)
Motor Control Register 1 (Motor1)
Write
Read
Write
Read
sub-CPU
sub-CPU
motor/tacho
bit detector
0D
Motor Mode Select Register 2 (Motor2)
Write
Read
Write
Read
Write
Read/Write
Read/Write
motor/tacho
bit detector
motor/tacho
0E
Motor Control Register 3 (Motor3)
0F
10
11
Motor Control Register 4 (Motor4)
Motor Control Register 5 (Motor5)
Motor Control Register 6 (Motor6)
motor/tacho
motor/tacho
motor/tacho