
2000 Mar 21
27
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.5.9
V
ITERBI
D
ETECTOR
S
ETTING
R
EGISTER
(V
ITSET
)
Thisregistercontrolsanadvanceddataslicerforimproved
bit detector performance.
An adaptive slicer performs a second slice operation.
This has a higher bandwidth than the first slicer.
If switched on, the run length 2 push-back circuit pushes
all run length two symbols to run length 3. The circuit will
determine which transition was most likely in error and
shift transition on that edge.
To avoid advanced detector hang-up, caused by a
detection level that is too high and is not brought down, a
Watchdog counter on the slicer level is installed.
The Watchdog counter is a counter that counts on the
front-end PLL clock.
If rl1 or a rl2 received: count + stepsize
Elsif no transition: count + 1
Elsif transition on a valid runlength: count
8
Elsif (count > maxcount): reset count.
Stepsize and maxcount can be set by writing to the VitSet
register. On a reset of the counter the slice level is also
reset.
Table 45
Viterbi Detector Setting Register (address 16H) - WRITE
Table 46
Description of VitSet bits
Table 47
Selection of Watchdog count step
7.5.10
M
OTOR
C
ONTROL
R
EGISTER
1 (M
OTOR
1)
When read this register holds the 8-bit advanced slicer compensation value.
7
6
5
4
3
2
1
0
AdSliceON
AdDetON
FEndAutoSON
RL2PB
WDog
MaxCnt
WDogCnt.1
WDogCnt.0
BIT
SYMBOL
DESCRIPTION
7
6
AdSliceON
AdDetON
If AdSliceON = 0, then slicer reset (to logic 0). If AdSliceON = 1, then slicer active.
If AdDetON = 0, then advanced bit detector off. If AdDetON = 1, then advanced bit
detector on.
If FEndAutoSON = 0, then auto-scaling in front-end Hold mode. If FEndAutoSON = 1,
then auto-scaling in front-end on.
If RL2PB = 0, then run length 2 push-back off. If RL2PB = 1, then run length 2
push-back on.
If WDog = 0, then slicer Watchdog is off. If WDog = 1, then slicer Watchdog is on.
If MaxCnt = 0, then maxcount is 1024. If MaxCnt = 1, then maxcount is 2048.
These 2 bits select the Watchdog count step; see Table 47.
5
FEndAutoSON
4
RL2PB
3
2
1
0
WDog
MaxCnt
WDogCnt.1
WDogCnt.0
WDogCnt.1
WDogCnt.0
WATCHDOG COUNT STEP
0
0
1
1
0
1
0
1
32
64
128
256