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參數(shù)資料
| 型號： | SAA7392 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Channel encoder/decoder CDR60(通道編碼器/譯碼器) |
| 中文描述： | 信道編碼器/解碼器CDR60（通道編碼器/譯碼器） |
| 文件頁數(shù)： | 33/76頁 |
| 文件大?。?/td> | 246K |
| 代理商： | SAA7392 |
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2000 Mar 21
33
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.8.2
F
ORMAT
The digital audio output consists of 32-bit words (subframes) transmitted in biphasemark code (two transitions for a
logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384.
Table 61
Digital audio output subframe format
Table 62
Channel status bit assignment
BIT
FIELD NAME
DESCRIPTION
0 to 3
sync
The sync word is formed by violation of the biphase rule and therefore does not
contain any data. Its length is equivalent to 4 data bits. The 3 different sync patterns
indicate the following situations:
Sync B: Start of a block (384 words), word contains left sample
Sync M: Word contains left sample (no block start)
Sync W: Word contains right sample.
These bits are not used; normally zero.
Left and right samples are transmitted alternately. The first 4 bits not used (always
zero); 2’s compliment; LSB = bit 12 and MSB = bit 27.
If validity flag = 1, audio samples are flagged if an error has been detected but was
uncorrectable. This flag remains the same even if data is taken after concealment.
Subcode bits Q until W from the subcode section are transmitted via the user data
bit. This data is asynchronous with the block rate.
The channel status bit is the same for left and right words. Therefore, a block of
384 words contains 192 channel status bits. The category code is always CD. The bit
assignment is shown in Table 62.
Even parity for bits 4 to 30.
4 to 7
8 to 27
auxiliary
audio sample
28
validity flag
29
user data
30
channel status
31
parity bit
BIT
FIELD NAME
DESCRIPTION
0 to 4
control
Bits 1 to 4 copied from register Output2. Bit 2 is logic 1 when copy permitted. Bit 3 is
logic 1 when recording has pre-emphasis
always zero
CD: bit 8 = logic 1, all other bits = logic 0
set by register Output2:
10 = level I
00 = level II
01 = level III
always zero
5 to 7
8 to 15
28 to 29
reserved mode
category code
clock accuracy
16 to 27,
30 to 191
remaining
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