參數(shù)資料
型號: SAA6712E
廠商: NXP SEMICONDUCTORS
元件分類: 數(shù)學處理器
英文描述: ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85%
中文描述: GRAPHICS PROCESSOR, PBGA292
封裝: 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292
文件頁數(shù): 9/64頁
文件大?。?/td> 228K
代理商: SAA6712E
1999 Aug 25
9
Philips Semiconductors
Preliminary specification
XGA RGB to TFT graphics engine
SAA6712E
PBG7
PBG6
PBG5
PBG4
PBG3
PBG2
PBG1
PBG0
PBB7
PBB6
PBB5
PBB4
PBB3
PBB2
PBB1
PBB0
SCL
SDA
SAD
OVCLK
OVVS
OVHS
OVACT
OVA0
OVA1
OVA2
OVB0
OVB1
OVB2
MCLKO
RAS
CAS
Y7
V8
W8
Y8
V9
W9
U9
Y9
V10
W10
Y10
Y11
U11
W11
V11
Y12
V18
W18
Y17
Y16
W16
V15
V16
Y14
V13
W13
Y15
V14
W14
A17
A18
C17
panel interface
panel interface
panel interface
panel interface
panel interface
panel interface
panel interface
panel interface
panel interface
panel interface
panel interface
panel interface
panel interface
panel interface
panel interface
panel interface
I
2
C-bus interface
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
input
input/output
input
output
output
output
input
input
input
input
input
input
input
output
output
output
panel port B green channel
panel port B blue channel
I
2
C-bus interface clock line
I
2
C-bus interface data line
I
2
C-bus address select: 0 = 74H, 1 = 76H
overlay port clock
overlay port vertical sync
overlay port horizontal sync
overlay port pixel active
overlay port input pixel A
overlay
overlay
overlay
overlay
overlay
overlay
overlay
overlay
overlay
overlay
memory interface
memory interface
memory interface
overlay port input pixel B
memory clock output
memory Row Address Strobe (RAS) signal (active LOW)
memory Column Address Strobe (CAS) signal
(active LOW)
memory Write Enable (WE) signal (active LOW)
memory data mask (active LOW)
WE
DQM
D16
T17
memory interface
memory interface
output
output
SYMBOL
Pin
PORT
I/O
(1)
DESCRIPTION
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