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參數(shù)資料
| 型號： | SAA6712E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% |
| 中文描述： | GRAPHICS PROCESSOR, PBGA292 |
| 封裝： | 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292 |
| 文件頁數(shù)： | 35/64頁 |
| 文件大?。?/td> | 228K |
| 代理商： | SAA6712E |
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1999 Aug 25
35
Philips Semiconductors
Preliminary specification
XGA RGB to TFT graphics engine
SAA6712E
OSD overlay port
G
ENERAL CONFIGURATION
OSD overlay port activation
Overlay information will not be inserted into data stream
Overlay information will be inserted into data stream
Sync pulse generation
No sync pulses will be generated
Sync pulses will be generated
Clock edge for sampling
Data sampling at falling edge of clock at pin OVCLK
Data sampling at rising edge of clock at pin OVCLK
Clock gating
OVCLK always enabled
OVCLK enabled only during internal active video processing
Horizontal sync polarity
Active LOW horizontal sync pulse at pin OVHS
Active HIGH horizontal sync pulse at pin OVHS
Vertical sync polarity
Active LOW vertical sync pulse at pin OVVS
Active HIGH vertical sync pulse at pin OVVS
Overlay port active pixel qualifier polarity
Active LOW qualifier signal at pin OVACT
Active HIGH qualifier signal at pin OVACT
Overlay port clock polarity
Sync pulse change with respect to falling edge at pin OVCLK
Sync pulse change with respect to rising edge at pin OVCLK
99
W
D0
logic 0
logic 1
D1
logic 0
logic 1
D2
logic 0
logic 1
D3
logic 0
logic 1
D4
logic 0
logic 1
D5
logic 0
logic 1
D6
logic 0
logic 1
D7
logic 0
logic 1
O
VERLAY HORIZONTAL SYNC START
Start of horizontal sync pulse with respect to left frame border
100 and 101
W
D10 to D0
O
VERLAY HORIZONTAL SYNC LENGTH
Length of horizontal sync pulse
102 and 103
W
D10 to D0
O
VERLAY HORIZONTAL SYNC LATENCY
Delay between start of horizontal sync and valid overlay data
104
W
D7 to D0
O
VERLAY WINDOW HORIZONTAL LENGTH
Horizontal length of overlay region
105 and 106
W
D10 to D0
O
VERLAY WINDOW VERTICAL OFFSET
Vertical offset of overlay region
107 and 108
W
D10 to D0
O
VERLAY WINDOW VERTICAL LENGTH
Vertical length of overlay region
109 and 110
W
D10 to D0
NAME
SUBADDRESS
R/W
DATA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA6713AH | XGA analog input flat panel controller |
| SAA6713H | XGA dual input flat panel controller |
| SAA7110 | Digital Multistandard Colour Decoder(數(shù)字多標(biāo)準(zhǔn)彩色譯碼器) |
| SAA7111 | Video Input Processor VIP |
| SAA7120H | Digital video encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA6713AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713AH/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA analog input flat panel controller |
| SAA6713H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6713H/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6721 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SXGA RGB to TFT graphics engine |
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