參數(shù)資料
型號: SAA6712E
廠商: NXP SEMICONDUCTORS
元件分類: 數(shù)學(xué)處理器
英文描述: ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85%
中文描述: GRAPHICS PROCESSOR, PBGA292
封裝: 27 X 27 MM, 1.75 MM HEIGHT, PLASTIC, SOT-489-1, BGA-292
文件頁數(shù): 53/64頁
文件大?。?/td> 228K
代理商: SAA6712E
1999 Aug 25
53
Philips Semiconductors
Preliminary specification
XGA RGB to TFT graphics engine
SAA6712E
8.12.2
F
RAME GENERATION
The output frame contains three main regions:
Blanking region
Border region
Active video region.
The blanking region contains all front and back porch as
well as the synchronization intervals. The border region is
visible on the panel and is used for positioning the active
video region inside this visible area. To ensure a great
flexibility in the ‘sync to input’ mode there are 3 different
horizontal length counters (h_len_blank, h_len_border,
h_len_active) with independent length control
(see Fig.17).
A maximum value must be programmed in h_max_len
which is the upper limit for line lengthening during
activated control mechanism. In free running mode all
3 counters should be programmed with the same
minimum values.
If no border is needed, because the active video region
covers the visible area of the panel, the active video length
counters should point to the same positions as the border
length counters. Then the active video length counters
have a higher priority.
The border colour inserted by the output interface is the
same as the blank colour in the memory interface;
blank_colour_red, blank_colour_green,
blank_colour_blue.
Fig.17 Output frame and timing.
handbook, full pagewidth
MHB262
active video
border
blanking
PHS
PVS
starting point
h_de_start
h_active_start
h_de_end
h_hs_end
h_hs_start
v_vs_end
v_start
v_end
v_active
h_len_blank
h_len_active
h_max_len
h_len_border
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SAA6721 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SXGA RGB to TFT graphics engine